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135

ATmega8515(L)

2512A–AVR–04/02

Double Speed Operation

(U2X)

Thetransferrate can be doubledbysetting the U2Xbit in UCSRA. Setting thisbit only

has effect for theasynchronous operation. Set thisbit to zero when using synchronous

operation.

Setting thisbit will reducethe divisor of the baudrate dividerfrom 16 to 8, effectively

doubling thetransferrate for asynchronouscommunication. Note however that the

receiverwill in thiscaseonly use half the number ofsamples(reducedfrom 16 to 8)for

data sampling andclock recovery, and thereforeamoreaccurate baudrate setting and

system clock are requiredwhen this modeis used. For thetransmitter, thereareno

downsides.

External Clock Externalclocking is usedbythe synchronousslave modes of operation. The description

in thissection refers to Figure 64 fordetails.

Externalclock input from the XCK pin issampledbya synchronization register to mini-

mizethe chanceof meta-stability.The output from the synchronization register must

then pass through an edge detectorbeforeitcan beusedbythetransmitter and

receiver.Thisprocess introduces atwo CPUclock perioddelay and thereforethemaxi-

mum externalXCKclock frequency islimitedbythe following equation:

Note that f

osc

depends on the stability of the system clock source. Itis therefore recom-

mended to add some margin to avoidpossible loss ofdata due to frequency variations.

Synchronous Clock Operation When synchronous modeis used (UMSEL = 1), the XCK pin will beused as eitherclock

input (Slave) orclock output (Master).The dependency between the clock edges and

data sampling ordata change is the same. The basicprincipleis that data input (on

RxD) issampled at theopposite XCK clock edge of theedge the data output (TxD) is

changed.

Figure 65. SynchronousMode XCK Timing.

The UCPOL bit UCRSC selectswhich XCK clock edge is usedfordata sampling and

which is usedfordata change. AsFigure 65 shows, when UCPOL iszerothe data will

be changed at rising XCK edge andsampled at falling XCK edge. If UCPOL isset, the

data will be changed at falling XCK edge andsampled at rising XCK edge.

XCK

OSC

-----------

RxD / TxD

XCK

RxD / TxD

XCK

UCPOL = 0

UCPOL = 1

Sample

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