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8048B–AVR–03/09
ATtiny43U
7.1 Sleep Modes ....................................................................................................31
7.2 Software BOD Disable .....................................................................................32
7.3 Power Reduction Register ...............................................................................32
7.4 Minimizing Power Consumption ......................................................................33
7.5 Register Description ........................................................................................34
8 Power Supply and On-Chip Boost Converter ...................................... 36
8.1 Overview ..........................................................................................................36
8.2 Modes of Operation .........................................................................................37
8.3 Output Voltage versus Load Current ...............................................................40
8.4 Overload Behaviour .........................................................................................42
8.5 Software Control of Boost Converter ...............................................................42
8.6 Component Selection ......................................................................................43
8.7 Typical Applications .........................................................................................46
8.8 Characteristics .................................................................................................46
8.9 Potential Limitations ........................................................................................46
8.10 Bypassing the Boost Converter .......................................................................46
8.11 Register Description ........................................................................................47
9 System Control and Reset .................................................................... 48
9.1 Resetting the AVR ...........................................................................................48
9.2 Reset Sources .................................................................................................49
9.3 Power-on Reset ...............................................................................................49
9.4 External Reset .................................................................................................50
9.5 Brown-out Detection ........................................................................................50
9.6 Watchdog Reset ..............................................................................................51
9.7 Internal Voltage Reference ..............................................................................51
9.8 Watchdog Timer ..............................................................................................51
9.9 Register Description ........................................................................................54
10 Interrupts ................................................................................................ 57
10.1 Interrupt Vectors ..............................................................................................57
10.2 External Interrupts ...........................................................................................58
10.3 Register Description ........................................................................................59
11 I/O Ports .................................................................................................. 62
11.1 Introduction ......................................................................................................62
11.2 Ports as General Digital I/O .............................................................................63
11.3 Alternate Port Functions ..................................................................................67
- Features 1
- 4. AVR CPU Core 7
- Initial Value00000000 9
- ATtiny43U 10
- 4.6 Stack Pointer 11
- 5. Memories 15
- 6.3 System Clock Prescaler 27
- 7.1 Sleep Modes 31
- 0 1 ADC Noise Reduction 35
- 1 0 Power-down 35
- 11Reserved 35
- SM1 SM0 Sleep Mode 35
- START MODE 41
- 8.6 Component Selection 43
- 8.11 Register Description 47
- 9.2 Reset Sources 49
- 9.3 Power-on Reset 49
- 9.6 Watchdog Reset 51
- 9.8 Watchdog Timer 51
- 10. Interrupts 57
- 10.3 Register Description 59
- DATA B U S 63
- INSTRUCTIONS 65
- SYNC LATCH 65
- SYSTEM CLK 65
- 11.3 Alternate Port Functions 67
- 12.1 Features 79
- 12.2 Overview 79
- 12.5 Output Compare Unit 81
- DATA BU S 83
- (Toggle) 85
- MAX - 1 MAX BOTTOM BOTTOM + 1 89
- 13.3 Register Description 99
- 14.3 Functional Descriptions 101
- 8048B–AVR–03/09 103
- A B D EC F 105
- 14.4 Alternative USI Usage 107
- 14.5 Register Descriptions 107
- Initial Value 0 0 0 0 0 0 0 0 109
- Bit 7 6 5 4 3 2 1 0 109
- 0x0E (0x2E) 109
- 0x10 (0x30) MSB LSB USIBR 111
- Read/Write R R R R R R R R 111
- 15.2 Register Description 113
- 16.1 Features 115
- 16.2 Overview 115
- 16.7 ADC Noise Canceler 121
- Output Code 123
- 16.11 ADC Conversion Result 125
- 16.12 Temperature Measurement 125
- 17.1 Features 131
- 17.2 Overview 131
- 17.3 Physical Interface 131
- Bit 76543210 135
- Rd ––––––LB2LB1 135
- 18.9 Register Description 137
- 19. Memory Programming 139
- 19.7 Serial Programming 151
- 20.2 DC Characteristics 155
- 20.4 Clock Characteristics 157
- Gain Calibration) 161
- = 5V ± 10% 163
- 21.1 Boost Converter 165
- 22. Register Summary 167
- 23. Instruction Set Summary 169
- 24. Ordering Information 171
- 25.2 20S2 173
- 27.1 Rev. 8048B-03/09 175
- 27.2 Rev. 8048A-02/09 175
- Table of Contents 177
- Headquarters International 182
- Product Contact 182
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