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8048B–AVR–03/09
ATtiny43U
To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and
repeat the procedure above. If successful, the contents of the destination register are as follows.
Refer to Table 19-4 on page 140 for detailed description and mapping of the Fuse High Byte.
To read the Fuse Extended Byte (FEB), replace the address in the Z-pointer with 0x0002 and
repeat the previous procedure. If successful, the contents of the destination register are as
follows.
Refer to Table 19-3 on page 140 for detailed description and mapping of the Fuse Extended
Byte.
18.6.3 Reading Device Signature Imprint Table from Firmware
To read the contents of the device signature imprint table, follow the below procedure:
1. Load the Z-pointer with the table index.
2. Set RSIG and SPMEN bits in SPMCSR.
3. Issue an LPM instruction within three clock cycles.
4. Read table data from the LPM destination register.
See program example below.
Note: See “Code Examples” on page 6.
If successful, the contents of the destination register are as described in section “Device Signa-
ture Imprint Table” on page 141.
Bit 76543210
Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0
Bit 76543210
Rd FEB7 FEB6 FEB5 FEB4 FEB3 FEB2 FEB1 FEB0
Assembly Code Example
DSIT_read:
; Uses Z-pointer as table index
ldi ZH, 0
ldi ZL, 1
; Preload SPMCSR bits into R16, then write to SPMCSR
ldi r16, (1<<RSIG)|(1<<SPMEN)
out SPMCSR, r16
; Issue LPM. Table data will be returned into r17
lpm r17, Z
ret
- Features 1
- 4. AVR CPU Core 7
- Initial Value00000000 9
- ATtiny43U 10
- 4.6 Stack Pointer 11
- 5. Memories 15
- 6.3 System Clock Prescaler 27
- 7.1 Sleep Modes 31
- 0 1 ADC Noise Reduction 35
- 1 0 Power-down 35
- 11Reserved 35
- SM1 SM0 Sleep Mode 35
- START MODE 41
- 8.6 Component Selection 43
- 8.11 Register Description 47
- 9.2 Reset Sources 49
- 9.3 Power-on Reset 49
- 9.6 Watchdog Reset 51
- 9.8 Watchdog Timer 51
- 10. Interrupts 57
- 10.3 Register Description 59
- DATA B U S 63
- INSTRUCTIONS 65
- SYNC LATCH 65
- SYSTEM CLK 65
- 11.3 Alternate Port Functions 67
- 12.1 Features 79
- 12.2 Overview 79
- 12.5 Output Compare Unit 81
- DATA BU S 83
- (Toggle) 85
- MAX - 1 MAX BOTTOM BOTTOM + 1 89
- 13.3 Register Description 99
- 14.3 Functional Descriptions 101
- 8048B–AVR–03/09 103
- A B D EC F 105
- 14.4 Alternative USI Usage 107
- 14.5 Register Descriptions 107
- Initial Value 0 0 0 0 0 0 0 0 109
- Bit 7 6 5 4 3 2 1 0 109
- 0x0E (0x2E) 109
- 0x10 (0x30) MSB LSB USIBR 111
- Read/Write R R R R R R R R 111
- 15.2 Register Description 113
- 16.1 Features 115
- 16.2 Overview 115
- 16.7 ADC Noise Canceler 121
- Output Code 123
- 16.11 ADC Conversion Result 125
- 16.12 Temperature Measurement 125
- 17.1 Features 131
- 17.2 Overview 131
- 17.3 Physical Interface 131
- Bit 76543210 135
- Rd ––––––LB2LB1 135
- 18.9 Register Description 137
- 19. Memory Programming 139
- 19.7 Serial Programming 151
- 20.2 DC Characteristics 155
- 20.4 Clock Characteristics 157
- Gain Calibration) 161
- = 5V ± 10% 163
- 21.1 Boost Converter 165
- 22. Register Summary 167
- 23. Instruction Set Summary 169
- 24. Ordering Information 171
- 25.2 20S2 173
- 27.1 Rev. 8048B-03/09 175
- 27.2 Rev. 8048A-02/09 175
- Table of Contents 177
- Headquarters International 182
- Product Contact 182
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