Rainbow-electronics Atmega169L Manuale Utente Scaricare il pdf (Pagina 132)

100

101

132

ATmega169V/L

2514A–AVR–08/02

Timer/Counter Timing

Diagrams

The following figures show the Timer/Counter in synchronous mode, and the timer clock

(clk

) is therefore shown as a clock enable signal. In asynchronous mode, clk

I/O

should

be replaced by the Timer/Counter Oscillator clock. The figures include information on

when interrupt flags are set. Figure 59 contains timing data for basic Timer/Counter

operation. The figure shows the count sequence close to the MAX value in all modes

other than phase correct PWM mode.

Figure 59. Timer/Counter Timing Diagram, no Prescaling

Figure 60 shows the same timing data, but with the prescaler enabled.

Figure 60. Timer/Counter Timing Diagram, with Prescaler (f

clk_I/O

/8)

Figure 61 shows the setting of OCF2A in all modes except CTC mode.

clk

(clk

I/O

/1)

TOVn

clk

I/O

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

TOVn

TCNTn

MAX - 1 MAX BOTTOM BOTTOM + 1

clk

I/O

clk

(clk

I/O

/8)

1 2 ... 127 128 129 130 131 132 133 134 135 136 137 ... 316 317

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