Rainbow-electronics Atmega169L Manuale Utente

1Features• High Performance, Low Power AVR®8-Bit Microcontroller• Advanced RISC Architecture– 130 Powerful Instructions – Most Single Clock Cycle Exec

10ATmega169V/L2514A–AVR–08/02• Bit0–C:CarryFlagThe Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruc-tion Set Descr

100ATmega169V/L2514A–AVR–08/02Timer/Counter ClockSourcesThe Timer/Counter can be clocked by an internal or an external clock source. The clocksource i

101ATmega169V/L2514A–AVR–08/02how waveforms are generated on the Output Compare outputs OC1x. For more detailsabout advanced counting sequences and wa

102ATmega169V/L2514A–AVR–08/02The ICR1 Register can only be written when using a Waveform Generation mode thatutilizes the ICR1 Register for defining

103ATmega169V/L2514A–AVR–08/02Output Compare Units The 16-bit comparator continuously compares TCNT1 with theOutput Compare Regis-ter(OCR1x). If TCNT

104ATmega169V/L2514A–AVR–08/02(Buffer or Compare) Register is only changed by a write operation (the Timer/Counterdoes not update this register automa

105ATmega169V/L2514A–AVR–08/02Compare Match OutputUnitTheCompare Output mode(COM1x1:0) bits have two functions. The Waveform Gener-ator uses the COM1x

106ATmega169V/L2514A–AVR–08/02Compare Output Mode andWaveform GenerationThe Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and

107ATmega169V/L2514A–AVR–08/02Clear Timer on CompareMatch (CTC) ModeInClear Timer on CompareorCTCmode(WGM13:0=4or12),theOCR1AorICR1Register are used t

108ATmega169V/L2514A–AVR–08/02Fast PWM Mode Thefast Pulse Width Modulationor fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) pro-vides a high frequency P

109ATmega169V/L2514A–AVR–08/02When changing the TOP value the program must ensure that the new TOP value ishigher or equal to the value of all of the

11ATmega169V/L2514A–AVR–08/02The X-register, Y-register, andZ-registerThe registers R26..R31 have some added functions to their general purpose usage.

110ATmega169V/L2514A–AVR–08/02Phase Correct PWM Mode Thephase correct Pulse Width Modulationor phase correct PWM mode (WGM13:0 = 1,2, 3, 10, or 11) pr

111ATmega169V/L2514A–AVR–08/02ICF1 flag is set accordingly at the same timer clock cycle as the OCR1x Registers areupdated with the double buffer valu

112ATmega169V/L2514A–AVR–08/02Phase and Frequency CorrectPWM ModeThephase and frequency correct Pulse Width Modulation,or phase and frequency cor-rect

113ATmega169V/L2514A–AVR–08/02The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as theOCR1x Registers are updated with the d

114ATmega169V/L2514A–AVR–08/02Timer/Counter TimingDiagramsThe Timer/Counter is a synchronous design and the timer clock (clkT1)isthereforeshown as a c

115ATmega169V/L2514A–AVR–08/02Figure 50. Timer/Counter Timing Diagram, no PrescalingFigure 51 shows the same timing data, but with the prescaler enabl

116ATmega169V/L2514A–AVR–08/0216-bit Timer/CounterRegister DescriptionTimer/Counter1 ControlRegister A – TCCR1A• Bit 7:6 – COM1A1:0: Compare Output Mo

117ATmega169V/L2514A–AVR–08/02Table 57 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to thephase correct or the phase and frequen

118ATmega169V/L2514A–AVR–08/02Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality

119ATmega169V/L2514A–AVR–08/02(ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt isenabled.When the ICR1 is used as T

12ATmega169V/L2514A–AVR–08/02Instruction ExecutionTimingThis section describes the general access timing concepts for instruction execution. TheAVR CP

120ATmega169V/L2514A–AVR–08/02A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in ClearTimer on Compare match (CTC) mo

121ATmega169V/L2514A–AVR–08/02Input Capture Register 1 –ICR1H and ICR1LThe Input Capture is updated with the counter (TCNT1) value each time an event

122ATmega169V/L2514A–AVR–08/02Timer/Counter1 Interrupt FlagRegister – TIFR1• Bit 5 – ICF1: Timer/Counter1, Input Capture FlagThis flag is set when a c

123ATmega169V/L2514A–AVR–08/028-bit Timer/Counter2with PWM andAsynchronousOperationTimer/Counter2 is a general purpose, single channel, 8-bit Timer/Co

124ATmega169V/L2514A–AVR–08/02ment) its value. The Timer/Counter is inactive when no clock source is selected. Theoutput from the Clock Select logic i

125ATmega169V/L2514A–AVR–08/02top Signalizes that TCNT2 has reached maximum value.bottom Signalizes that TCNT2 has reached minimum value (zero).Depend

126ATmega169V/L2514A–AVR–08/02The OCR2A Register is double buffered when using any of the Pulse Width Modulation(PWM) modes. For the Normal and Clear

127ATmega169V/L2514A–AVR–08/02Compare Match OutputUnitThe Compare Output mode (COM2A1:0) bits have two functions. The Waveform Gener-ator uses the COM

128ATmega169V/L2514A–AVR–08/02Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Comparepins, is defined

129ATmega169V/L2514A–AVR–08/02compare match. The counter will then have to count to its maximum value (0xFF) andwrap around starting at 0x00 before th

13ATmega169V/L2514A–AVR–08/02moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see“Boot Loader Support – Read-While-Write

130ATmega169V/L2514A–AVR–08/02The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. Ifthe interrupt is enabled, the interru

131ATmega169V/L2514A–AVR–08/02Figure 58. Phase Correct PWM Mode, Timing DiagramThe Timer/Counter Overflow Flag (TOV2) is set each time the counter rea

132ATmega169V/L2514A–AVR–08/02Timer/Counter TimingDiagramsThe following figures show the Timer/Counter in synchronous mode, and the timer clock(clkT2)

133ATmega169V/L2514A–AVR–08/02Figure 61. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8)Figure 62 shows the setting of OCF

134ATmega169V/L2514A–AVR–08/028-bit Timer/CounterRegister DescriptionTimer/Counter ControlRegister A– TCCR2A• Bit 7 – FOC2A: Force Output Compare AThe

135ATmega169V/L2514A–AVR–08/02• Bit 5:4 – COM2A1:0: Compare Match Output Mode AThese bits control the Output Compare pin (OC2A) behavior. If one or bo

136ATmega169V/L2514A–AVR–08/02• Bit 2:0 – CS22:0: Clock SelectThe three Clock Select bits select the clock source to be used by the Timer/Counter, see

137ATmega169V/L2514A–AVR–08/02Asynchronous operationof the Timer/CounterAsynchronous StatusRegister – ASSR• Bit 4 – EXCLK: Enable External Clock Input

138ATmega169V/L2514A–AVR–08/02Asynchronous Operation ofTimer/Counter2When Timer/Counter2 operates asynchronously, some considerations must be taken.•

139ATmega169V/L2514A–AVR–08/02• Description of wake up from Power-save or Extended Standby mode when the timeris clocked asynchronously: When the inte

14ATmega169V/L2514A–AVR–08/02When using the SEI instruction to enable interrupts, the instruction following SEI will beexecuted before any pending int

140ATmega169V/L2514A–AVR–08/02Timer/Counter2 Interrupt FlagRegister – TIFR2• Bit 1 – OCF2A: Output Compare Flag 2 AThe OCF2A bit is set (one) when a c

141ATmega169V/L2514A–AVR–08/02Timer/Counter Prescaler Figure 63. Prescaler for Timer/Counter2The clock source for Timer/Counter2 is named clkT2S.clkT2

142ATmega169V/L2514A–AVR–08/02Serial PeripheralInterface – SPIThe Serial Peripheral Interface (SPI) allows high-speed synchronous data transferbetween

143ATmega169V/L2514A–AVR–08/02When configured as a Master, the SPI interface has no automatic control of the SS line.This must be handled by user soft

144ATmega169V/L2514A–AVR–08/02The following code examples show how to initialize the SPI as a Master and how to per-form a simple transmission. DDR_SP

145ATmega169V/L2514A–AVR–08/02The following code examples show how to initialize the SPI as a Slave and how to per-form a simple reception.Note: 1. Th

146ATmega169V/L2514A–AVR–08/02SS Pin FunctionalitySlave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. WhenSSi

147ATmega169V/L2514A–AVR–08/02• Bit 4 – MSTR: Master/Slave SelectThis bit selects Master SPI mode when written to one, and Slave SPI mode when written

148ATmega169V/L2514A–AVR–08/02SPI Status Register – SPSR• Bit 7 – SPIF: SPI Interrupt FlagWhen a serial transfer is complete, the SPIF flag is set. An

149ATmega169V/L2514A–AVR–08/02Data Modes There are four combinations of SCK phase and polarity with respect to serial data,which are determined by con

15ATmega169V/L2514A–AVR–08/02AVR ATmega169MemoriesThis section describes the different memories in the ATmega169. The AVR architecturehas two main mem

150ATmega169V/L2514A–AVR–08/02USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter(USART) is a highly flexible serial comm

151ATmega169V/L2514A–AVR–08/02The dashed boxes in the block diagram separate the three main parts of the USART(listed from the top): Clock Generator,

152ATmega169V/L2514A–AVR–08/02Figure 69. Clock Generation Logic, Block DiagramSignal description:txclk Transmitter clock (Internal Signal).rxclk Recei

153ATmega169V/L2514A–AVR–08/02Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)BAUD Baud rate (in bits per second, bps

154ATmega169V/L2514A–AVR–08/02Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clockinput (Sl

155ATmega169V/L2514A–AVR–08/02Sp Stop bit, always high.IDLE No transfers on the communication line (RxD or TxD). An IDLE line must behigh.The frame fo

156ATmega169V/L2514A–AVR–08/02The following simple USART initialization code examples show one assembly and oneC function that are equal in functional

157ATmega169V/L2514A–AVR–08/02Data Transmission – TheUSART TransmitterThe USART Transmitter is enabled by setting theTransmit Enable(TXEN) bit in theU

158ATmega169V/L2514A–AVR–08/02Sending Frames with 9 DataBitIf 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit inUC

159ATmega169V/L2514A–AVR–08/02Transmitter Flags andInterruptsThe USART Transmitter has two flags that indicate its state: USART Data RegisterEmpty (UD

16ATmega169V/L2514A–AVR–08/02SRAM Data Memory Figure 9 shows how the ATmega169 SRAM Memory is organized.The ATmega169 is a complex microcontroller wit

160ATmega169V/L2514A–AVR–08/02Data Reception – TheUSART ReceiverThe USART Receiver is enabled by writing the Receive Enable (RXEN) bit in theUCSRB Reg

161ATmega169V/L2514A–AVR–08/02Receiving Frames with 9 DataBitsIf 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit inUCS

162ATmega169V/L2514A–AVR–08/02The receive function example reads all the I/O Registers into the Register File beforeany computation is done. This give

163ATmega169V/L2514A–AVR–08/02Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Typeof Parity Check to be

164ATmega169V/L2514A–AVR–08/02Asynchronous ClockRecoveryThe clock recovery logic synchronizes internal clock to the incoming serial frames. Fig-ure 72

165ATmega169V/L2514A–AVR–08/02Figure 74 shows the sampling of the stop bit and the earliest possible beginning of thestart bit of the next frame.Figur

166ATmega169V/L2514A–AVR–08/02The recommendations of the maximum receiver baud rate error was made under theassumption that the Receiver and Transmitt

167ATmega169V/L2514A–AVR–08/02Multi-processorCommunication ModeSetting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a fil-tering

168ATmega169V/L2514A–AVR–08/02USART RegisterDescriptionUSART I/O Data Register –UDRThe USART Transmit Data Buffer Register and USART Receive Data Buff

169ATmega169V/L2514A–AVR–08/02• Bit 5 – UDRE: USART Data Register EmptyThe UDRE flag indicates if the transmit buffer (UDR) is ready to receive new da

17ATmega169V/L2514A–AVR–08/02Data Memory Access Times This section describes the general access timing concepts for internal memory access.The interna

170ATmega169V/L2514A–AVR–08/02USART Control and StatusRegister B – UCSRB• Bit 7 – RXCIE: RX Complete Interrupt EnableWriting this bit to one enables i

171ATmega169V/L2514A–AVR–08/02USART Control and StatusRegister C – UCSRC• Bit 6 – UMSEL: USART Mode SelectThis bit selects between asynchronous and sy

172ATmega169V/L2514A–AVR–08/02• Bit 2:1 – UCSZ1:0: Character SizeThe UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits(Ch

173ATmega169V/L2514A–AVR–08/02Examples of Baud RateSettingFor standard crystal and resonator frequencies, the most commonly used baud rates forasynchr

174ATmega169V/L2514A–AVR–08/02Table 80. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)BaudRate(bps)fosc= 3.6864 MHz fo

175ATmega169V/L2514A–AVR–08/02Table 81. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)BaudRate(bps)fosc= 8.0000 MHz fo

176ATmega169V/L2514A–AVR–08/02Table 82. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)BaudRate(bps)fosc= 16.0000 MHz f

177ATmega169V/L2514A–AVR–08/02Universal SerialInterface – USIThe Universal Serial Interface, or USI, provides the basic hardware resources neededfor s

178ATmega169V/L2514A–AVR–08/02The Two-wire clock control unit can generate an interrupt when a start condition isdetected on the Two-wire bus. It can

179ATmega169V/L2514A–AVR–08/02The Three-wire mode timing is shown in Figure 77. At the top of the figure is a USCKcycle reference. One bit is shifted

18ATmega169V/L2514A–AVR–08/02The EEPROM AddressRegister – EEARH and EEARL• Bits 15..9 – Res: Reserved BitsThese bits are reserved bits in the ATmega16

180ATmega169V/L2514A–AVR–08/02The following code demonstrates how to use the USI module as a SPI Master with max-imum speed (fsck = fck/2):SPITransfer

181ATmega169V/L2514A–AVR–08/02Note that the first two instructions is for initialization only and needs only to be executedonce.These instructions set

182ATmega169V/L2514A–AVR–08/02Figure 79. Two-wire Mode, Typical Timing DiagramReferring to the timing diagram (Figure 79.), a bus transfer involves th

183ATmega169V/L2514A–AVR–08/02Start Condition Detector The start condition detector is shown in Figure 80. The SDA line is delayed (in the rangeof 50

184ATmega169V/L2514A–AVR–08/02Note that the corresponding Data Direction Register to the pin must be set to one forenabling data output from the Shift

185ATmega169V/L2514A–AVR–08/02Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input(USCK/SCL) are can still be used by

186ATmega169V/L2514A–AVR–08/02Note: 1. The DI and USCK pins are renamed toSerial Data(SDA) andSerial Clock(SCL)respectively to avoid confusion between

187ATmega169V/L2514A–AVR–08/02• Bit 3..2 – USICS1..0: Clock Source SelectThese bits set the clock source for the Shift Register and counter. The data

188ATmega169V/L2514A–AVR–08/02Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and nega-tive pin AIN1. When

189ATmega169V/L2514A–AVR–08/02• Bit 6 – ACBG: Analog Comparator Bandgap SelectWhen this bit is set, a fixed bandgap reference voltage replaces the pos

19ATmega169V/L2514A–AVR–08/02• Bit 1 – EEWE: EEPROM Write EnableTheEEPROMWriteEnableSignalEEWEisthewritestrobetotheEEPROM.Whenaddress and data are cor

190ATmega169V/L2514A–AVR–08/02Analog ComparatorMultiplexed InputIt is possible to select any of the ADC7..0 pins to replace the negative input to the

191ATmega169V/L2514A–AVR–08/02Analog to DigitalConverterFeatures • 10-bit Resolution• 0.5 LSB Integral Non-linearity• ± 2 LSB Absolute Accuracy• TBD -

192ATmega169V/L2514A–AVR–08/02Figure 82. Analog to Digital Converter Block SchematicOperation The ADC converts an analog input voltage to a 10-bit dig

193ATmega169V/L2514A–AVR–08/02The ADC generates a 10-bit result which is presented in the ADC Data Registers,ADCH and ADCL. By default, the result is

194ATmega169V/L2514A–AVR–08/02conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In thismode the ADC will perform successi

195ATmega169V/L2514A–AVR–08/02In Free Running mode, a new conversion will be started immediately after the conver-sion completes, while ADSC remains h

196ATmega169V/L2514A–AVR–08/02Figure 88. ADC Timing Diagram, Free Running ConversionDifferential Channels When using differential channels, certain as

197ATmega169V/L2514A–AVR–08/02Changing Channel orReference SelectionThe MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a tem-

198ATmega169V/L2514A–AVR–08/02ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC.Single ended c

199ATmega169V/L2514A–AVR–08/02Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 89. An analogsource

2ATmega169V/L2514A–AVR–08/02Pin Configurations Figure 1. Pinout ATmega169Disclaimer Typical values contained in this data sheet are based on simulatio

20ATmega169V/L2514A–AVR–08/02The following code examples show one assembly and one C function for writing to theEEPROM. The examples assume that inter

200ATmega169V/L2514A–AVR–08/02Analog Noise CancelingTechniquesDigital circuitry inside and outside the device generates EMI which might affect theaccu

201ATmega169V/L2514A–AVR–08/02ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREFin 2nsteps (LSBs). Th

202ATmega169V/L2514A–AVR–08/02Figure 93. Integral Non-linearity (INL)• Differential Non-linearity (DNL): The maximum deviation of the actual code widt

203ATmega169V/L2514A–AVR–08/02ADC Conversion ResultAfter the conversion is complete (ADIF is high), the conversion result can be found inthe ADC Resul

204ATmega169V/L2514A–AVR–08/02Example: ADMUX = 0xFB (ADC3 - ADC2, 1.1V reference, left adjusted result)Voltage on ADC3 is 300 mV, voltage on ADC2 is 5

205ATmega169V/L2514A–AVR–08/02• Bits 4:0 – MUX4:0: Analog Channel Selection BitsThe value of these bits selects which combination of analog inputs are

206ATmega169V/L2514A–AVR–08/02ADC Control and StatusRegister A – ADCSRA• Bit 7 – ADEN: ADC EnableWriting this bit to one enables the ADC. By writing i

207ATmega169V/L2514A–AVR–08/02• Bits 2:0 – ADPS2:0: ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and t

208ATmega169V/L2514A–AVR–08/02• ADC9:0: ADC Conversion ResultThese bits represent the result from the conversion, as detailed in “ADC ConversionResult

209ATmega169V/L2514A–AVR–08/02LCD Controller The LCD Controller/driver is intended for monochrome passive liquid crystal display(LCD) with up to four

21ATmega169V/L2514A–AVR–08/02The next code examples show assembly and C functions for reading the EEPROM. Theexamples assume that interrupts are contr

210ATmega169V/L2514A–AVR–08/02Figure 96. Block Diagram LCD ModuleLCD Clock Cources The LCD Controller can be clocked by an internal synchronous or an

211ATmega169V/L2514A–AVR–08/02Addressing COM0 starts a frame by driving opposite phase with large amplitude out onCOM0 compared to none addressed COM

212ATmega169V/L2514A–AVR–08/02Figure 98. Driving a LCD with One Common Terminal1/2Dutyand1/2Bias For LCD with two common terminals (1/2 duty) a more c

213ATmega169V/L2514A–AVR–08/021/3Dutyand1/3Bias 1/3 bias is usually recommended for LCD with three common terminals (1/3 duty).Waveform is shown in Fi

214ATmega169V/L2514A–AVR–08/02Low Power Waveform To reduce toggle activity and hence power consumption a low power waveform can beselected by writing

215ATmega169V/L2514A–AVR–08/02LCD UsageLCD Initialization Prior to enabling the LCD some initialization must be preformed. The initialization pro-cess

216ATmega169V/L2514A–AVR–08/02Note: 1. The example code assumes that the part specific header file is included.Assembly Code Example(1)LCD_Init:; Use

217ATmega169V/L2514A–AVR–08/02Before a re-initialization is done, the LCD controller/driver should be disabledUpdating the LCD Display memory (LCDDR0,

218ATmega169V/L2514A–AVR–08/02Note: 1. The example code assumes that the part specific header file is included.Assembly Code Example(1)LCD_disable:; W

219ATmega169V/L2514A–AVR–08/02LCD Control and StatusRegister A – LCDCRA• Bit 7 – LCDEN: LCD EnableWriting this bit to one enables the LCD Controller/D

22ATmega169V/L2514A–AVR–08/02I/O Memory The I/O space definition of the ATmega169 is shown in “Register Summary” on page302.All ATmega169 I/Os and per

220ATmega169V/L2514A–AVR–08/02LCD Control and StatusRegister B – LCDCRB• Bit 7 – LCDCS: LCD Clock SelectWhen this bit is written to zero, the system c

221ATmega169V/L2514A–AVR–08/02• Bits 2:0 – LCDPM2:0: LCD Port MaskThe LCDPM2:0 bits determine the number of port pins to be used as segment drivers.Th

222ATmega169V/L2514A–AVR–08/02• Bit 3 – Res: Reserved BitThis bit is reserved bit in the ATmega169 and will always read as zero.• Bits 2:0 – LCDCD2:0:

223ATmega169V/L2514A–AVR–08/02LCD Contrast ControlRegister – LCDCCR• Bits 7:4 – Res: Reserved BitsThese bits are reserved bits in the ATmega169 and wi

224ATmega169V/L2514A–AVR–08/02LCD Memory Mapping Write a LCD memory bit to one and the corresponding segment will be energized (visi-ble). Unused LCD

225ATmega169V/L2514A–AVR–08/02JTAG Interface andOn-chip DebugSystemFeatures • JTAG (IEEE std. 1149.1 Compliant) Interface• Boundary-scan Capabilities

226ATmega169V/L2514A–AVR–08/02The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT –which is not provided.When the JTAGEN Fus

227ATmega169V/L2514A–AVR–08/02Figure 105. TAP Controller State DiagramTAP Controller The TAP controller is a 16-state finite state machine that contro

228ATmega169V/L2514A–AVR–08/02state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating thestate machine.• At the TMS input, appl

229ATmega169V/L2514A–AVR–08/02A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Spe-cific JTAG Instructions” on page 2

23ATmega169V/L2514A–AVR–08/02System Clock andClock OptionsClock Systems and theirDistributionFigure 11 presents the principal clock systems in the AVR

230ATmega169V/L2514A–AVR–08/02On-chip Debug RelatedRegister in I/O MemoryOn-chip Debug Register –OCDRThe OCDR Register provides a communication channe

231ATmega169V/L2514A–AVR–08/02IEEE 1149.1 (JTAG)Boundary-scanFeatures • JTAG (IEEE std. 1149.1 compliant) Interface• Boundary-scan Capabilities Accord

232ATmega169V/L2514A–AVR–08/02Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Regis-ter is selected as

233ATmega169V/L2514A–AVR–08/02Reset Register The Reset Register is a test data register used to reset the part. Since the AVR tri-statesPort Pins when

234ATmega169V/L2514A–AVR–08/02EXTEST; 0x0 Mandatory JTAG instruction for selecting the Boundary-scan Chain as data register fortesting circuitry exter

235ATmega169V/L2514A–AVR–08/02Boundary-scan RelatedRegister in I/O MemoryMCU Control Register –MCUCRThe MCU Control Register contains control bits for

236ATmega169V/L2514A–AVR–08/02Figure 108. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.DQ DQG0101DQ DQG01010101DQ DQG01Port Pi

237ATmega169V/L2514A–AVR–08/02Figure 109. General Port Pin Schematic DiagramScanning the RESET Pin The RESET pin accepts 5V active low logic for stand

238ATmega169V/L2514A–AVR–08/02Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RCOscillator, E

239ATmega169V/L2514A–AVR–08/02Scanning the AnalogComparatorThe relevant Comparator signals regarding Boundary-scan are shown in Figure 112.The Boundar

24ATmega169V/L2514A–AVR–08/02ADC Clock – clkADCThe ADC is provided with a dedicated clock domain. This allows halting the CPU andI/O clocks in order t

240ATmega169V/L2514A–AVR–08/02Scanning the ADC Figure 114 shows a block diagram of the ADC with all relevant control and observe sig-nals. The Boundar

241ATmega169V/L2514A–AVR–08/02Table 105. Boundary-scan Signals for the ADC(1)SignalNameDirectionas Seenfrom theADC DescriptionRecommen-ded Inputwhen n

242ATmega169V/L2514A–AVR–08/02G10 Input Enable 10x gain 0 0G20 Input Enable 20x gain 0 0GNDEN Input Ground the negativeinput to comparatorwhen true00H

243ATmega169V/L2514A–AVR–08/02Note: 1. Incorrect setting of the switches in Figure 114 will make signal contention and maydamage the part. There are s

244ATmega169V/L2514A–AVR–08/02As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3when the power supply is 5.0V and

245ATmega169V/L2514A–AVR–08/02ATmega169 Boundary-scan OrderTable 107 shows the Scan order between TDI and TDO when the Boundary-scan chainis selected

246ATmega169V/L2514A–AVR–08/02168 MUXEN_3 ADC167 MUXEN_2166 MUXEN_1165 MUXEN_0164 NEGSEL_2163 NEGSEL_1162 NEGSEL_0161 PASSEN160 PRECH159 ST158 VCCREN1

247ATmega169V/L2514A–AVR–08/02132 PB0.Control Port B131 PB0.Pullup_Enable130 PB1.Data129 PB1.Control128 PB1.Pullup_Enable127 PB2.Data126 PB2.Control12

248ATmega169V/L2514A–AVR–08/0296 EXTCLK (XTAL1) Clock input and Osillators for the mainclock(Observe-only)95 OSCCK94 RCCK93 OSC32CK92 PD0.Data Port D9

249ATmega169V/L2514A–AVR–08/0260 PC0.Pullup_Enable Port C59 PC1.Data58 PC1.Control57 PC1.Pullup_Enable56 PC2.Data55 PC2.Control54 PC2.Pullup_Enable53

25ATmega169V/L2514A–AVR–08/02Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which canbe configured f

250ATmega169V/L2514A–AVR–08/02Boundary-scanDescription LanguageFilesBoundary-scan Description Language (BSDL) files describe Boundary-scan capabledevi

251ATmega169V/L2514A–AVR–08/02Boot Loader Support– Read-While-WriteSelf-ProgrammingThe Boot Loader Support provides a real Read-While-Write Self-Progr

252ATmega169V/L2514A–AVR–08/02Note that the user software can never read any code that is located inside the RWWsection during a Boot Loader software

253ATmega169V/L2514A–AVR–08/02Figure 115. Read-While-Write vs. No Read-While-WriteRead-While-Write(RWW) SectionNo Read-While-Write (NRWW) SectionZ-poi

254ATmega169V/L2514A–AVR–08/02Figure 116. Memory SectionsNote: 1. The parameters in the figure above are given in Table 113 on page 263.Boot Loader Lo

255ATmega169V/L2514A–AVR–08/02Note: 1. “1” means unprogrammed, “0” means programmedNote: 1. “1” means unprogrammed, “0” means programmedEntering the B

256ATmega169V/L2514A–AVR–08/02Store Program MemoryControl and Status Register –SPMCSRThe Store Program Memory Control and Status Register contains the

257ATmega169V/L2514A–AVR–08/02• Bit 1 – PGERS: Page EraseIf this bit is written to one at the same time as SPMEN, the next SPM instruction withinfour

258ATmega169V/L2514A–AVR–08/02Figure 117. Addressing the Flash During SPM(1)Note: 1. The different variables used in Figure 117 are listed in Table 11

259ATmega169V/L2514A–AVR–08/02Performing Page Erase bySPMTo execute Page Erase, set up the address in the Z-pointer, write “X0000011” toSPMCSR and exe

26ATmega169V/L2514A–AVR–08/02Notes: 1. These options should only be used when not operating close to the maximum fre-quency of the device, and only if

260ATmega169V/L2514A–AVR–08/02Setting the Boot Loader LockBits by SPMTo set the Boot Loader Lock bits, write the desired data to R0, write “X0001001”

261ATmega169V/L2514A–AVR–08/02When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPMinstruction is executed within three cycle

262ATmega169V/L2514A–AVR–08/02Simple Assembly CodeExample for a Boot Loader;-the routine writes one page of data from RAM to Flash; the first data loc

263ATmega169V/L2514A–AVR–08/02ret; re-enable the RWW sectionldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)call Do_spmrjmp ReturnDo_spm:; check for

264ATmega169V/L2514A–AVR–08/02Note: 1. Z15:Z14: always ignoredZ0: should be zero for all SPM commands, byte select for the LPM instruction.See “Addres

265ATmega169V/L2514A–AVR–08/02MemoryProgrammingProgram And DataMemory Lock BitsThe ATmega169 provides six Lock bits which can be left unprogrammed (“1

266ATmega169V/L2514A–AVR–08/02Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.2. “1” means unprogrammed, “0” mea

267ATmega169V/L2514A–AVR–08/02Note: 1. The SPIEN Fuse is not accessible in serial programming mode.2. The default value of BOOTSZ1..0 results in maxim

268ATmega169V/L2514A–AVR–08/02Latching of Fuses The fuse values are latched when the device enters programming mode and changes ofthe fuse values will

269ATmega169V/L2514A–AVR–08/02Table 121. Pin Name MappingSignal Name inProgramming Mode Pin Name I/O FunctionRDY/BSYPD1 O0: Device is busy programming

27ATmega169V/L2514A–AVR–08/02Note: 1. These options should only be used if frequency stability at start-up is not important forthe applicationCalibrat

270ATmega169V/L2514A–AVR–08/02Serial Programming PinMappingTable 124. Command Byte Bit CodingCommand Byte Command Executed1000 0000 Chip Erase0100 000

271ATmega169V/L2514A–AVR–08/02Parallel ProgrammingEnter Programming Mode The following algorithm puts the device in parallel programming mode:1. Apply

272ATmega169V/L2514A–AVR–08/021. SetXA1,XA0to“00”. This enables address loading.2. Set BS1 to “0”. This selects low address.3. Set DATA = Address low

273ATmega169V/L2514A–AVR–08/02Figure 119. Addressing the Flash Which is Organized in Pages(1)Note: 1. PCPAGE and PCWORD are listed in Table 125 on pag

274ATmega169V/L2514A–AVR–08/02K: Repeat 3 through 5 until the entire buffer is filled.L: Program EEPROM page1. Set BS to “0”.2. Give WRa negative puls

275ATmega169V/L2514A–AVR–08/02Programming the Fuse LowBitsThe algorithm for programming the Fuse Low bits is as follows (refer to “Programmingthe Flas

276ATmega169V/L2514A–AVR–08/02Reading the Fuse and LockBitsThe algorithm for reading the Fuse and Lock bits is as follows (refer to “Programmingthe Fl

277ATmega169V/L2514A–AVR–08/02Parallel ProgrammingCharacteristicsFigure 124. Parallel Programming Timing, Including some General TimingRequirementsFig

278ATmega169V/L2514A–AVR–08/02Figure 126. Parallel Programming Timing, Reading Sequence (within the Same Page)with Timing Requirements(1)Note: 1. The

279ATmega169V/L2514A–AVR–08/02Notes: 1. tWLRHis valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lockbits commands.2. tWLRH_CEis val

28ATmega169V/L2514A–AVR–08/02Oscillator Calibration Register– OSCCAL• Bits 6..0 – CAL6..0: Oscillator Calibration ValueWriting the calibration byte to

280ATmega169V/L2514A–AVR–08/02Serial ProgrammingAlgorithmWhen writing serial data to the ATmega169, data is clocked on the rising edge of SCK.When rea

281ATmega169V/L2514A–AVR–08/02Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading theaddress location be

282ATmega169V/L2514A–AVR–08/02Note: a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t

283ATmega169V/L2514A–AVR–08/02Serial ProgrammingCharacteristicsFigure 129. Serial Programming TimingNote: 1. 2 tCLCLfor fck<12MHz,3tCLCLfor fck>

284ATmega169V/L2514A–AVR–08/02The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It canalso be used as an idle state b

285ATmega169V/L2514A–AVR–08/02PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via theJTAG port. The 15-

286ATmega169V/L2514A–AVR–08/02Reset Register The Reset Register is a Test Data Register used to reset the part during programming. Itis required to re

287ATmega169V/L2514A–AVR–08/02Programming CommandRegisterThe Programming Command Register is a 15-bit register. This register is used to seri-ally shi

288ATmega169V/L2514A–AVR–08/02Table 132. JTAG Programming InstructionSeta = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte,

289ATmega169V/L2514A–AVR–08/025d. Read Data Byte 0110011_bbbbbbbb0110010_000000000110011_00000000xxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_oooooooo6a. E

29ATmega169V/L2514A–AVR–08/02External Clock To drive the device from an external clock source, XTAL1 should be driven as shown inFigure 13. To run the

290ATmega169V/L2514A–AVR–08/02Notes: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (whi

291ATmega169V/L2514A–AVR–08/02Figure 133. State Machine Sequence for Changing/Reading the Data WordFlash Data Byte Register The Flash Data Byte Regist

292ATmega169V/L2514A–AVR–08/02including the first read byte. This ensures that the first data is captured from the firstaddress set up by PROG_COMMAND

293ATmega169V/L2514A–AVR–08/02Programming the Flash 1. Enter JTAG instruction PROG_COMMANDS.2. Enable Flash write using programming instruction 2a.3.

294ATmega169V/L2514A–AVR–08/02gram counter after each word is read. Note that Capture-DR comes before theshift-DR state. Hence, the first byte which i

295ATmega169V/L2514A–AVR–08/02Reading the Fuses and LockBits1. Enter JTAG instruction PROG_COMMANDS.2. Enable Fuse/Lock bit read using programming ins

296ATmega169V/L2514A–AVR–08/02Electrical CharacteristicsAbsolute Maximum Ratings*Operating Temperature ... -55°Cto+125°

297ATmega169V/L2514A–AVR–08/02Note: 1. “Max” means the highest value where the pin is guaranteed to be read as low2. “Min” means the lowest value wher

298ATmega169V/L2514A–AVR–08/02External Clock DriveWaveformsFigure 135. External Clock Drive WaveformsExternal Clock DriveSPI TimingCharacteristicsSee

299ATmega169V/L2514A–AVR–08/02Figure 136. SPI Interface Timing Requirements (Master Mode)Figure 137. SPI Interface Timing Requirements (Slave Mode)MOS

3ATmega169V/L2514A–AVR–08/02OverviewThe ATmega169 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executingp

30ATmega169V/L2514A–AVR–08/02Timer/Counter Oscillator ATmega169 share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1and XTAL2. This me

300ATmega169V/L2514A–AVR–08/02ADC Characteristics – Preliminary DataLCD Controller Characteristics – Preliminary DataTable 135. ADC CharacteristicsSym

301ATmega169V/L2514A–AVR–08/02ATmega169 TypicalCharacteristics –Preliminary DataThe following charts show typical behavior. These figures are not test

302ATmega169V/L2514A–AVR–08/02Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page(0xFF) Reserved – – – – – – – –(0xFE) L

303ATmega169V/L2514A–AVR–08/02(0xBF) Reserved – – – – – – – –(0xBE) Reserved – – – – – – – –(0xBD) Reserved – – – – – – – –(0xBC) Reserved – – – – – –

304ATmega169V/L2514A–AVR–08/02(0x7D) Reserved – – – – – – – –(0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 204(0x7B) ADCSRB ADHSM ACME ADTS2

305ATmega169V/L2514A–AVR–08/02Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory

306ATmega169V/L2514A–AVR–08/02Instruction Set SummaryMnemonics Operands Description Operation Flags #ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr

307ATmega169V/L2514A–AVR–08/02BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2BRID k Branch if Interrupt Disabled if ( I =

308ATmega169V/L2514A–AVR–08/02POP Rd Pop Register from Stack Rd ← STACK None 2MCU CONTROL INSTRUCTIONSNOP No Operation None 1SLEEP Sleep (see specific

309ATmega169V/L2514A–AVR–08/02Ordering InformationNote: This device can also be supplied in wafer form. Please contact your local Atmel sales office f

31ATmega169V/L2514A–AVR–08/02frequency than the maximum frequency of the device at the present operating condi-tions. The device is shipped with the C

310ATmega169V/L2514A–AVR–08/02Packaging Information64APIN 1 ID0.80(0.0315) BSC16.25(0.640)SQSQ15.75(0.620)0.45(0.018)0.30(0.012)14.10(0.555)13.90(0.54

iATmega169V/L2514A–AVR–08/02Table of ContentsFeatures...

iiATmega169V/L2514A–AVR–08/02System Control and Reset... 36Internal Voltage Reference ..

iiiATmega169V/L2514A–AVR–08/02Modes of Operation ... 128Timer/C

ivATmega169V/L2514A–AVR–08/02JTAG Interface and On-chip Debug System ... 225Overview...

vATmega169V/L2514A–AVR–08/02ADC Characteristics – Preliminary Data... 300LCD Controller Charac

viATmega169V/L2514A–AVR–08/02

Printed on recycled paper.© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those expressly contain

32ATmega169V/L2514A–AVR–08/02Power Managementand Sleep ModesSleep modes enable the application to shut down unused modules in the MCU, therebysaving p

33ATmega169V/L2514A–AVR–08/02Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enterIdle mode, stopping the CPU b

34ATmega169V/L2514A–AVR–08/02The LCD controller and Timer/Counter2 can be clocked both synchronously and asyn-chronously in Power-save mode. The clock

35ATmega169V/L2514A–AVR–08/02Brown-out Detector If the Brown-out Detector is not needed by the application, this module should be turnedoff. If the Br

36ATmega169V/L2514A–AVR–08/02System Control andResetResetting the AVR During reset, all I/O Registers are set to their initial values, and the program

37ATmega169V/L2514A–AVR–08/02Figure 14. Reset LogicNotes: 1. Values are guidelines only. Actual values are TBD.2. The Power-on Reset will not work unl

38ATmega169V/L2514A–AVR–08/02Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-tion level is defined

39ATmega169V/L2514A–AVR–08/02External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longerthan the minimum pulse

4ATmega169V/L2514A–AVR–08/02The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly c

40ATmega169V/L2514A–AVR–08/02When the BOD is enabled, and VCCdecreases to a value below the trigger level (VBOT-in Figure 18), the Brown-out Reset is

41ATmega169V/L2514A–AVR–08/02• Bit 3 – WDRF: Watchdog Reset FlagThis bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or b

42ATmega169V/L2514A–AVR–08/02Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at1 MHz. This is the typical v

43ATmega169V/L2514A–AVR–08/02Watchdog Timer ControlRegister – WDTCR• Bits 7..5 – Res: Reserved BitsThese bits are reserved bits in the ATmega169 and w

44ATmega169V/L2514A–AVR–08/02The following code example shows one assembly and one C function for turning off theWDT. The example assumes that interru

45ATmega169V/L2514A–AVR–08/02Interrupts This section describes the specifics of the interrupt handling as performed inATmega169. For a general explana

46ATmega169V/L2514A–AVR–08/02Table 23 shows reset and Interrupt Vectors placement for the various combinations ofBOOTRST and IVSEL settings. If the pr

47ATmega169V/L2514A–AVR–08/02When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes andthe IVSEL bit in the MCUCR Register is se

48ATmega169V/L2514A–AVR–08/02When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and theIVSEL bit in the MCUCR Register is set

49ATmega169V/L2514A–AVR–08/02• Bit 0 – IVCE: Interrupt Vector Change EnableThe IVCE bit must be written to logic one to enable change of the IVSEL bit

5ATmega169V/L2514A–AVR–08/02Pin DescriptionsVCC Digital supply voltage.GND Ground.Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with in

50ATmega169V/L2514A–AVR–08/02I/O-PortsIntroduction All AVR ports have true Read-Modify-Write functionality when used as general digitalI/O ports. This

51ATmega169V/L2514A–AVR–08/02Note that enabling the alternate function of some of the port pins does not affect the useof the other pins in the port a

52ATmega169V/L2514A–AVR–08/02Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value ofDDRxn. Note that th

53ATmega169V/L2514A–AVR–08/02Consider the clock period starting shortly after the first falling edge of the system clock.The latch is closed when the

54ATmega169V/L2514A–AVR–08/02The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, anddefine the port pins from 4 to 7 as

55ATmega169V/L2514A–AVR–08/02Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure25 show

56ATmega169V/L2514A–AVR–08/02The following subsections shortly describe the alternate functions for each port, andrelate the overriding signals to the

57ATmega169V/L2514A–AVR–08/02MCU Control Register –MCUCR• Bit 4 – PUD: Pull-up DisableWhen this bit is written to one, the pull-ups in the I/O ports a

58ATmega169V/L2514A–AVR–08/02Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 29.The alternate pin configurat

59ATmega169V/L2514A–AVR–08/02• OC1B/PCINT14, Bit 6OC1B, Output Compare Match B output: The PB6 pin can serve as an external outputfor the Timer/Counte

6ATmega169V/L2514A–AVR–08/02resistors are activated. The Port F pins are tri-stated when a reset condition becomesactive, even if the clock is not run

60ATmega169V/L2514A–AVR–08/02• SCK/PCINT9 – Port B, Bit 1SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI isenabled as a

61ATmega169V/L2514A–AVR–08/02Alternate Functions of Port C The Port C has an alternate function as the SEG5:12 for the LCD ControllerTable 31. Overrid

62ATmega169V/L2514A–AVR–08/02Table 33 and Table 34 relate the alternate functions of Port C to the overriding signalsshown in Figure 25 on page 55.Tab

63ATmega169V/L2514A–AVR–08/02Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 35.The alternate pin configurat

64ATmega169V/L2514A–AVR–08/02Table 36 and Table 37 relates the alternate functions of Port D to the overriding signalsshown in Figure 25 on page 55.Ta

65ATmega169V/L2514A–AVR–08/02Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 38.• PCINT7 – Port E, Bit 7PCIN

66ATmega169V/L2514A–AVR–08/02• XCK/AIN0/PCINT2 – Port E, Bit 2XCK, USART External Clock. The Data Direction Register (DDE2) controls whether theclock

67ATmega169V/L2514A–AVR–08/02Note: 1. AIN0D and AIN1D is described in “Digital Input Disable Register 0 – DIDR0” on page190.Alternate Functions of Por

68ATmega169V/L2514A–AVR–08/02• TCK, ADC6 – Port F, Bit 6ADC6, Analog to Digital Converter, Channel 6.TDO, JTAG Test Data Out: Serial output data from

69ATmega169V/L2514A–AVR–08/02Alternate Functions of Port G The alternate pin configuration is as follows:The alternate pin configuration is as follows

7ATmega169V/L2514A–AVR–08/02AVR CPU CoreIntroduction This section discusses the AVR core architecture in general. The main function of theCPU core is

70ATmega169V/L2514A–AVR–08/02• SEG4 – Port G, Bit 2SEG4, LCD front plane 4• SEG13 – Port G, Bit 1SEG13, Segment driver 13• SEG14 – Port G, Bit 0SEG14,

71ATmega169V/L2514A–AVR–08/02Table 46. Overriding Signals for Alternate Functions in PG3:0SignalName PG3/T1/SEG24 PG2/SEG4 PG1/SEG13 PG0/SEG14PUOE LCD

72ATmega169V/L2514A–AVR–08/02Register Description forI/O-PortsPort A Data Register – PORTAPort A Data Direction Register– DDRAPort A Input Pins Addres

73ATmega169V/L2514A–AVR–08/02Port C Input Pins Address –PINCPort D Data Register – PORTDPort D Data Direction Register– DDRDPort D Input Pins Address

74ATmega169V/L2514A–AVR–08/02Port F Input Pins Address –PINFPort G Data Register – PORTGPort G Data Direction Register– DDRGPort G Input Pins Address

75ATmega169V/L2514A–AVR–08/02External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT15..0 pins.Observe that, if

76ATmega169V/L2514A–AVR–08/02External Interrupt MaskRegister – EIMSK• Bit 7 – PCIE1: Pin Change Interrupt Enable 1When the PCIE1 bit is set (one) and

77ATmega169V/L2514A–AVR–08/02• Bit 0 – INTF0: External Interrupt Flag 0When an edge or logic change on the INT0 pin triggers an interrupt request, INT

78ATmega169V/L2514A–AVR–08/028-bit Timer/Counter0with PWMTimer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. Themain feat

79ATmega169V/L2514A–AVR–08/02event will also set the Compare Flag (OCF0A) which can be used to generate an OutputCompare interrupt request.Definitions

8ATmega169V/L2514A–AVR–08/02the operation is executed, and the result is stored back in the Register File – in oneclock cycle.Six of the 32 registers

80ATmega169V/L2514A–AVR–08/02Depending of the mode of operation used, the counter is cleared, incremented, or dec-remented at each timer clock (clkT0)

81ATmega169V/L2514A–AVR–08/02The OCR0A Register is double buffered when using any of the Pulse Width Modulation(PWM) modes. For the normal and Clear T

82ATmega169V/L2514A–AVR–08/02Compare Match OutputUnitThe Compare Output mode (COM0A1:0) bits have two functions. The Waveform Gener-ator uses the COM0

83ATmega169V/L2514A–AVR–08/02Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Comparepins, is defined

84ATmega169V/L2514A–AVR–08/02to OCR0A is lower than the current value of TCNT0, the counter will miss the comparematch. The counter will then have to

85ATmega169V/L2514A–AVR–08/02The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. Ifthe interrupt is enabled, the interrup

86ATmega169V/L2514A–AVR–08/02Figure 32. Phase Correct PWM Mode, Timing DiagramThe Timer/Counter Overflow Flag (TOV0) is set each time the counter reac

87ATmega169V/L2514A–AVR–08/02Timer/Counter TimingDiagramsThe Timer/Counter is a synchronous design and the timer clock (clkT0)isthereforeshown as a cl

88ATmega169V/L2514A–AVR–08/02Figure 36 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.Figure 36. Timer/Counter Timing Diagram, Clear

89ATmega169V/L2514A–AVR–08/02Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-initions. However, the functionalit

9ATmega169V/L2514A–AVR–08/02Status Register The Status Register contains information about the result of the most recently executedarithmetic instruct

90ATmega169V/L2514A–AVR–08/02Table 52 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set tophase correct PWM mode.Note: 1. A special c

91ATmega169V/L2514A–AVR–08/02Output Compare Register A –OCR0AThe Output Compare Register A contains an 8-bit value that is continuously comparedwith t

92ATmega169V/L2514A–AVR–08/02Timer/Counter0 andTimer/Counter1PrescalersTimer/Counter1 and Timer/Counter0 share the same prescaler module, but theTimer

93ATmega169V/L2514A–AVR–08/02the edge detector uses sampling, the maximum frequency of an external clock it candetect is half the sampling frequency (

94ATmega169V/L2514A–AVR–08/0216-bitTimer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event man-agement), wave gen

95ATmega169V/L2514A–AVR–08/02Figure 39. 16-bit Timer/Counter Block Diagram(1)Note: 1. Refer to Figure 1 on page 2, Table 28 on page 58, and Table 34 o

96ATmega169V/L2514A–AVR–08/02also set the Compare Match Flag (OCF1A/B) which can be used to generate an OutputCompare interrupt request.The Input Capt

97ATmega169V/L2514A–AVR–08/02Accessing 16-bitRegistersThe TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVRCPU via the 8-b

98ATmega169V/L2514A–AVR–08/02Therefore, when both the main code and the interrupt code update the temporary regis-ter, the main code must disable the

99ATmega169V/L2514A–AVR–08/02The following code examples show how to do an atomic write of the TCNT1 Registercontents. Writing any of the OCR1A/B or I