ATmega163(L)
19
•
Bit 2 - N: Negative Flag
The negative flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set Description for
detailed information.
•
Bit 1 - Z: Zero Flag
The zero flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set Description for detailed
information.
•
Bit 0 - C: Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed
information.
Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from
an interrupt routine. This must be handled by software.
The Stack Pointer - SP
The ATmega163 Stack Pointer is implemented as two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D).
As the ATmega163 data memory has $460 locations, 11 bits are used.
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack
space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are
enabled. The Stack Pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed
onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack
with subroutine call and interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the
POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or
return from interrupt RETI.
Reset and Interrupt Handling
The ATmega163 provides 17 different interrupt sources. These interrupts and the separate reset vector, each have a sep-
arate program vector in the program memory space. All interrupts are assigned individual enable bits which must be set
(one) together with the I-bit in the status register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The
complete list of vectors is shown in Table 3. The list also determines the priority levels of the different interrupts. The lower
the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request
0, etc.
Bit 151413121110 9 8
$3E ($5E) - - - - - SP10 SP9 SP8 SPH
$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R R R R R R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000
00000000
(162 pagine)
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