
ATmega163(L)
105
Figure 68. PORTB Schematic Diagram (Pin PB6)
Figure 69. PORTB Schematic Diagram (Pin PB7)
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PB6
R
R
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
DDB6
PORTB6
SPE
MSTR
SPI SLAVE
OUT
SPI MASTER
IN
RL
RP
PUD
PUD: PULL-UP DISABLE
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PB7
R
R
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
DDB7
PORTB7
SPE
MSTR
SPI ClLOCK
OUT
SPI CLOCK
IN
RL
RP
PUD
PUD: PULL-UP DISABLE
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