Rainbow-electronics DS2141A Manuale Utente

Copyright 1995 by Dallas Semiconductor Corporation.All Rights Reserved. For important information regardingpatents and other intellectual property r

DS2141A021997 10/35PAYLOAD LOOPBACKWhen CCR1.1 is set to a 1, the DS2141A will be forcedinto Payload LoopBack (PLB). Normally, this loopbackis only e

DS2141A021997 11/35RSLC96 CCR2.1 Receive SLC–96 Enable. 0=SLC–96 disabled.1=SLC–96 enabled.RFDL CCR2.0 Receive Zero Destuffer Enable. 0=zero destuffer

DS2141A021997 12/35SEFE RIR.2 Severely Errored Framing Event. Set when 2 out of 6 framing bits arereceived in error.B8ZS RIR.1 B8ZS Code Word Detect.

DS2141A021997 13/35SR2: STATUS REGISTER 2 (21h)(MSB) (LSB)RMF TMF SEC RFDL TFDL RMTCH RAF LORCSYMBOL POSITION NAME AND DESCRIPTIONRMF SR2.7 Receive Mu

DS2141A021997 14/35RCL IMR1.1 Receive Carrier Loss. 0=interrupt masked.1=interrupt enabled.RLOS IMR1.0 Receive Loss of Sync. 0=interrupt masked.1=inte

DS2141A021997 15/355.0 ERROR COUNT REGISTERSThere is a set of three counters in the DS2141A that re-cord bipolar violations, errors in the CRC6 code w

DS2141A021997 16/35FECR: FRAME ERROR COUNT REGISTER (27h)(MSB) (LSB)FE7 FE6 FE5 FE4 FE3 FE2 FE1 FE0SYMBOL POSITION NAME AND DESCRIPTIONFE7 FECR.7 MSB

DS2141A021997 17/35RFDL: RECEIVE FDL REGISTER (28h)(MSB) (LSB)RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0SYMBOL POSITION NAME AND DESCRIPTIONRFDL7

DS2141A021997 18/35TFDL: TRANSMIT FDL REGISTER (7Eh)(MSB) (LSB)TFDL7 TFDL6 TFDL5 TFDL4 TFDL3 TFDL2 TFDL1 TFDL0SYMBOL POSITION NAME AND DESCRIPTIONTFDL

DS2141A021997 19/35Each Receive Signaling Register (RS1 to RS12) reportsthe incoming robbed bit signaling from eight DS0 chan-nels. In the ESF framin

BPV COUNTERSYNCHRONIZERALARM DETECTIONLOOP CODE DETECTORCRC/FRAME ERROR COUNTONE’S DENSITY MONITORSIGNALING EXTRACTIONPAYLOAD LOOPBACKTIMING CONTROL/F

DS2141A021997 20/35TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTERS (39h to 3Bh) (MSB) (LSB)CH8CH7 CH6 CH5 CH4 CH3 CH2 CH1CH16 CH15 CH14 CH13 CH12

DS2141A021997 21/359.0 CLOCK BLOCKING REGISTERSThe Receive Channel Blocking Registers(RCBR1/RCBR2/RCBR3) and the Transmit ChannelBlocking Registers (T

DS2141A021997 22/35386–bit elastic buffer either fills or empties, a controlledslip will occur. If th e buffer empties, then a full frame ofdata (193

DS2141A021997 23/3513.0 TIMING DIAGRAMSRECEIVE SIDE D4 TIMING12 345 67891011121 23 45FRAME#RSYNC1RSYNC2RSYNC3RLCLKRLINK4NOTES:1. RSYNC in the frame mo

DS2141A021997 24/351.544 MHz BOUNDARY TIMING (WITH ELASTIC STORE(S) ENABLED)SYSCLKTSER/RSERRSYNC1RSYNC2RCHCLKRCHBLK3CHANNEL 24 CHANNEL 1CHANNEL 23LSB

DS2141A021997 25/35RECEIVE SIDE BOUNDARY TIMING (WITH ELASTIC STORE(S) DISABLED)RCLKRPOS1,RNEGTSER/RSER1RSYNCRCHCLKRCHBLK2RLCLKRLINKLSB F MSB LSB MSB

DS2141A021997 26/35TRANSMIT SIDE ESF TIMINGFRAME#TSYNC1TSYNC2TSYNC3TLCLK4TLINK5TLCLK6TLINK71 2 3 4 5 6 7 8 9 1011 12131415161718192021222324NOTES:1. T

DS2141A021997 27/35TRANSMIT SIDE BOUNDARY TIMING (WITH ELASTIC STORE(S) DISABLED)TCLKTSER1TPOS,TNEG1TSYNC2TSYNC3TCHCLKCHANNEL 2LSB MSBLSB MSBFCHANNEL

DS2141A021997 28/35ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground –1.0V to +7.0VOperating Temperature 0°C to 70°CStorage Temperature –

DS2141A021997 29/35AC CHARACTERISTICS – PARALLEL PORT (0°C to 70°C; VDD = 5V + 10%)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESCycle Time tCYC250 nsPulse

DS2141A021997 3/35DS2141A FEATURES• parallel control port• large error counters• onboard dual 2–frame elastic store• FDL support circuitry• robbed–bit

DS2141A021997 30/35INTEL READ AC TIMING AC TIMINGALEWRRDCSAD0–AD7tCYCPWASHPWEHtASDtASEDtASLtDDRtCHtDHRtASDtCStAHLPWELINTEL WRITE AC TIMINGALEWRRDCSAD0

DS2141A021997 31/35MOTOROLA AC TIMINGASDSR/WAD0–AD7(READ)CSAD0–AD7(WRITE)PWASHPWELtCYCtRWStASDtRWHtDDRtDHRtCHtCStAHLtASLtDHWtDSWtAHLtASLtASEDPWEHAC CH

DS2141A021997 32/35RECEIVE SIDE AC TIMINGSYSCLKRCLKRSERRPOS,RNEGRCHCLKRCHBLKRSYNC1RSYNC2RLCLKRLINKtRtDDtFtCLtCHtPtHDtSUtDDtSUtPWtDDtDDtDDtDDF–BITNOTES

DS2141A021997 33/35AC CHARACTERISTICS – TRANSMIT SIDE (0°C to 70°C; VDD = 5V + 10%)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESTCLK Period tP648 nsTCLK Pu

DS2141A021997 34/35DS2141A T1 CONTROLLER (600 MIL) 40–PIN DIPBDACKG HJEF140INCHESDIM MIN MAXA 2.040 2.070B 0.530 0.560C 0.145 0.155D 0.600 0.625E 0.01

DS2141A021997 35/35DS2141AQ T1 CONTROLLER 44–PIN PLCCCA1A2 ABB1.075 MAXN1.150MAXNOTE 1D1DCH1EE1e1E2D2NOTE1: PIN 1 IDENTIFIER TO BE LOCATED IN ZONE IN

DS2141A021997 4/35PIN DESCRIPTIONTYPESYMBOL25 RSYNC I/O Receive Sync. An extracted pulse, one RCLK wide, is output at thispin which identifies either

DS2141A021997 5/35DS2141A REGISTER MAPADDRESS R/W REGISTER NAME20 R/W Status Register 121 R/W Status Register 222 R/W Receive Information Register23 R

DS2141A021997 6/352.0 PARALLEL PORTThe DS2141A is controlled via a multiplexed bidirectionaladdress/data bus by an external microcontroller or micro-p

DS2141A021997 7/35RCR2: RECEIVE CONTROL REGISTER 2 (2Ch)(MSB) (LSB)RCS RZBTSI RSDW RSM RSIO RD4YM FSBE BPVCRSSYMBOL POSITION NAME AND DESCRIPTIONRCS R

DS2141A021997 8/35TCR1: TRANSMIT CONTROL REGISTER 1 (35h)(MSB) (LSB)ODF TFPT TCPT RBSE GB7S TLINK TBL TYELSYMBOL POSITION NAME AND DESCRIPTIONODF TCR1

DS2141A021997 9/35TSDW TCR2.4 TSYNC Double–Wide. 0=do not pulse double–wide in signaling frames.1=do pulse double–wide in signaling frames.(note: this