Rainbow-electronics DS2143Q Manuale Utente

Copyright 1997 by Dallas Semiconductor Corporation.All Rights Reserved. For important information regardingpatents and other intellectual property r

DS2143/DS2143Q031397 10/40TSA1 TCR1.2 Transmit Signaling All Ones. 0 = normal operation 1 = force timeslot 16 in every frame to all onesTSM TCR1.1 TSY

DS2143/DS2143Q031397 11/40TG802 CCR.5 Transmit G.802 Enable. See Section 13 for details. 0 = do not force TCHBLK high during bit 1 of timeslot 26 1 =

DS2143/DS2143Q031397 12/40The SR1 and SR2 registers have the unique ability toinitiate a hardware interrupt via the INT1 and INT2 pinsrespectively. E

DS2143/DS2143Q031397 13/40CRC4 SYNC COUNTERThe CRC4 Sync Counter increments each time the 8msCRC4 multiframe search times out. The counter iscleared

DS2143/DS2143Q031397 14/40ALARM CRITERIA Table 3ALARM SET CRITERIA CLEAR CRITERIAITUSPEC.RSA1(receive signalingall ones)over 16 consecutive frames (o

DS2143/DS2143Q031397 15/40LOTC SR2.2 Loss of Transmit Clock. Set when the TCLK pin has not transitioned forone channel time (or 3.9 µs). Will force

DS2143/DS2143Q031397 16/40IMR2: INTERRUPT MASK REGISTER 2 (Address=17 Hex)(MSB) (LSB)RMF RAF TMF SEC TAF LOTC RCMF LORCSYMBOL POSITION NAME AND DESCRI

DS2143/DS2143Q031397 17/40BPVCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address=00 Hex)BPVCR2: LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address=0

DS2143/DS2143Q031397 18/40or CRC4 level; it will continue to count if loss of syncoccurs at the CAS level.6.0 Sa DATA LINK CONTROL ANDOPERATIONThe DS

DS2143/DS2143Q031397 19/40SYMBOL POSITION NAME AND DESCRIPTIONX RS1.0/1/3 Spare BitsY RS1.2 Remote Alarm Bit (integrated and reported in SR1.6)A(1) RS

DS2143/DS2143Q031397 2/401.0 INTRODUCTIONThe DS2143 E1 Controller has four main sections: thereceive side, the transmit side, the line interface contr

DS2143/DS2143Q031397 20/40Each Transmit Signaling Register (TS1 to TS16) con-tains the CAS bits for two timeslots that will be insertedinto the outgoi

DS2143/DS2143Q031397 21/409.0 CLOCK BLOCKING REGISTERSThe Receive Channel Blocking Registers(RCBR1/RCBR2/RCBR3/RCBR4) and the TransmitChannel Blocking

DS2143/DS2143Q031397 22/4010.0 ELASTIC STORE OPERATIONThe DS2143 has an onboard two frame (512 bits) elas-tic store. This elastic store can be enable

DS2143/DS2143Q031397 23/40RNAF: RECEIVE NON–ALIGN FRAME REGISTER (Address=1F Hex)(MSB) (LSB)Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8SYMBOL POSITION NAME AND DESCRIP

DS2143/DS2143Q031397 24/40Sa5 TNAF.3 Additional Bit 5.Sa6 TNAF.2 Additional Bit 6.Sa7 TNAF.1 Additional Bit 7.Sa8 TNAF.0 Additional Bit 8.12.0 LINE IN

DS2143/DS2143Q031397 25/40RECEIVE SIDE 1.544 MHZ BOUNDARY TIMING (WITH ELASTIC STORE ENABLED)SYSCLKRSER1RSYNC2RSYNC3RCHCLKRCHBLK4CHANNEL 24/32 CHANNEL

DS2143/DS2143Q031397 26/40RECEIVE SIDE BOUNDARY TIMING (WITH ELASTIC STORE DISABLED)RCLKRPOS,RNEG1RSER1RSYNCRCHCLKRCHBLK2RLCLK3RLINKLSB Si MSB LSB MSB

DS2143/DS2143Q031397 27/40G.802 TIMINGTIMESLOT# 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4R

DS2143/DS2143Q031397 28/40TRANSMIT SIDE BOUNDARY TIMINGTCLKTSER1TPOS,TNEG1TSYNC2TSYNC3TCHCLKCHANNEL 2CHANNEL 1CHANNEL 2CHANNEL 1CHANNEL 32TCHBLK4TLCLK

DS2143/DS2143Q031397 29/40TRANSMIT SIDE TIMING15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15FRAME#1612345614TSYNC1TSYNC2TCLK3TLINK3NOTES:1. TSYNC in the fr

DS2143/DS2143Q031397 3/40DS2143 BLOCK DIAGRAMHDB3 DECODERBPV COUNTERSYNCHRONIZERALARM DETECTIONCRC4 ERROR COUNTE–BIT COUNTSIGNALING EXTRACTIONAIS GENE

DS2143/DS2143Q031397 30/40DS2143 SYNCHRONIZATION FLOWCHARTPOWER UPRLOS=1FAS SYNCSYNC DECLAREDCRITERIA METFASSA=0CAS MULTIFRAMESEARCH (IF ENABLEDVIA CC

TSERTLINKTIDRTS0TS15AISGENERATIONTRANSMIT SIGNALLINGALL ONES(TCR1.2)TPOS,TNEGTAFTNAFTIMESLOT 0PASS–THROUGH(TCR1.6)Si BIT INSERTIONCONTROL(TCR1.3)Sa BI

DS2143/DS2143Q031397 32/40ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground –1.0V to +7.0VOperating Temperature 0°C to 70°CStorage Temper

DS2143/DS2143Q031397 33/40AC CHARACTERISTICS – PARALLEL PORT (0°C to 70°C; VDD = 5V + 10%)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESCycle Time tCYC250 n

DS2143/DS2143Q031397 34/40INTEL WRITE AC TIMINGALEWRRDCSAD0-AD7PWASHtASDtASLtCHtAHLtASDtASEDPWEHPWELtDSWtDHWtCStCYCINTEL READ AC TIMINGALEWRRDCSAD0-AD

DS2143/DS2143Q031397 35/40MOTOROLA AC TIMINGASDSR/WAD0-AD7(READ)CSAD0-AD7(WRITE)PWASHPWELtCYCtRWStASDtRWHtDDRtDHRtCHtCStAHLtASLtDHWtDSWtAHLtASLtASEDPW

DS2143/DS2143Q031397 36/40AC CHARACTERISTICS – TRANSMIT SIDE (0°C to 70°C; VDD = 5V + 10%)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESTCLK Period tP488 ns

DS2143/DS2143Q031397 37/40TRANSMIT SIDE AC TIMINGTCLKTPOS,TNEGTSERTCHCLKTCHBLKTSYNC1TSYNC2TLCLK3TLINK3tRtFtDDtCLtPtCHtSUtHDtDDtDDtDDtPWtSUtDDtHDtSUNOT

DS2143/DS2143Q031397 38/40RECEIVE SIDE AC TIMINGSYSCLKRCLKRSERRPOS,RNEGRCHCLKRCHBLKRSYNC1RSYNC2RLCLK3RLINK3tRtDDtFtCLtCHtPtHDtSUtDDtSUtPWtDDtDDtDDtDDN

DS2143/DS2143Q031397 39/40DS2143 E1 CONTROLLER (600 MIL) 40–PIN DIPBDACKG HJEF140INCHESDIM MIN MAXA 2.040 2.070B 0.530 0.560C 0.145 0.155D 0.600 0.625

DS2143/DS2143Q031397 4/40PIN DESCRIPTION Table 1PIN SYMBOL TYPE DESCRIPTION1 TCLK I Transmit Clock. 2.048 MHz primary clock. A clock must be applie

DS2143/DS2143Q031397 40/40DS2143 E1 CONTROLLER 44–PIN PLCCCA1A2 ABB1.075 MAXN1.150MAXNOTE 1D1DCH1EE1e1E2D2NOTE1: PIN 1 IDENTIFIER TO BE LOCATED IN ZO

DS2143/DS2143Q031397 5/40PIN DESCRIPTIONTYPESYMBOL30 LI_CLK O Serial Port Clock for the Line Interface. Connects directly to the SCLKinput pin on the

DS2143/DS2143Q031397 6/40DS2143 REGISTER MAPADDRESSA7 to A0HEX R/W REGISTER NAME00000000 00 R Bipolar Violation CountRegister 1.00000001 01 R Bipolar

DS2143/DS2143Q031397 7/40ADDRESSA7 to A0HEX R/W REGISTER NAME00111011 3B R Receive SignalingRegister 12.00111100 3C R Receive SignalingRegister 13.001

DS2143/DS2143Q031397 8/40RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex)(MSB) (LSB)RSMF RSM RSIO – – FRC SYNCE RESYNCSYMBOL POSITION NAME AND DESCRI

DS2143/DS2143Q031397 9/40RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex)(MSB) (LSB)Sa8S Sa7S Sa6S Sa5S Sa4S SCLKM ESE –SYMBOL POSITION NAME AND DESC