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HT49R70A-1
Rev. 1.00 16 December 4, 2001
The register states are summarized below:
Register Reset (Power On)
WDT Time-out
(Norma Operation)
RES
Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
TMR xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TMR0C 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u---
TMR1H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TMR1L xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TMR1C 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u---
Program Counter 0000H 0000H 0000H 0000H 0000H
MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
BP ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u
ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu
INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu
INTC1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu
RTCC --00 0111 --00 0111 --00 0111 --00 0111 --uu uuuu
PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
Note:
²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
Timer/Event Counter
Two timer/event counters are implemented in the
HT49R70A-1. One of them contains an 8-bit program-
mable count-up counter, the other contains a 16-bit pro
-
grammable count-up counter.
The Timer/Event Counter 0 clock source may come
from the system clock or system clock/4 or RTC time-out
signal or external source. System clock source or sys
-
tem clock/4 is selected by options.
The Timer/Event Counter 1 clock source may come
from TMR0 overflow or system clock or time base
time-out signal or system clock/4 or external source,
and the three former clock source is selected by options.
The external clock input allows the user to count exter
-
nal events, measure time intervals or pulse widths, or to
generate an accurate time base.
There are two registers related to the Timer/Event
Counter 0; TMR0 ([0DH]), TMR0C ([0EH]). Two physi
-
cal registers are mapped to TMR0 location; writing
TMR0 puts the starting value in the Timer/Event Coun
-
ter 0 register and reading TMR0 takes the contents of
the Timer/Event Counter 0. The TMR0C is a timer/event
counter control register, which defines some options.
There are three registers related to the Timer/Event
Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H).
Writing TMR1L will only put the written data to an inter-
nal lower-order byte buffer (8-bit) and writing TMR1H
will transfer the specified data and the contents of the
lower-order byte buffer to TMR1H and TMR1L regis
-
ters, respectively. The Timer/Event Counter 1 preload
register is changed by each writing TRM1H operations.
Reading TMR1H will latch the contents of TMR1H and
TMR1L counters to the destination and the lower-order
byte buffer, respectively. Reading the tMR1L will read
the contents of the lower-order byte buffer. The TMR1C
is the Timer/Event Counter 1 control register, which de
-
fines the operating mode, counting enable or disable
and an active edge.
The TN0 and TN1 bits define the operation mode. The
event count mode is used to count external events,
which means that the clock source is from an external
(TMR0, TMR1) pin. The timer mode functions as a nor
-
mal timer with the clock source coming from the internal
selected clock source. Finally, the pulse width measure
-
ment mode can be used to count the high or low level
duration of the external signal (TMR0, TMR1), and the
counting is based on the internal selected clock source.
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