Rainbow-electronics ATmega64L Manuale Utente Scaricare il pdf (Pagina 158)

158

ATmega16(L)

2466B–09/01

• Bit 0 - TXB8: Transmit Data Bit 8

TXB8 is the 9th data bit in the character to be transmitted when operating with serial

frames with 9 data bits. Must be written before writing the low bits to UDR.

USART Control and Status

The UCSRC register shares the same I/O location as the UBRRH register. See the

“Accessing UBRRH/ UCSRC Registers” on page 154 section which describes how to

access this register.

• Bit 7 - URSEL: Register Select

This bit selects between accessing the UCSRC or the UBRRH register. It is read as one

when reading UCSRC. The URSEL must be one when writing the UCSRC.

• Bit 6 - UMSEL: USART Mode Select

This bit selects between asynchronous and synchronous mode of operation.

• Bit 5:4 - UPM1:0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the transmit-

ter will automatically generate and send the parity of the transmitted data bits within

each frame. The receiver will generate a parity value for the incoming data and compare

it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSRA will be set.

• Bit 3 - USBS: Stop Bit Select

This bit selects the number of stop bits to be inserted by the transmitter. The receiver

ignores this setting.

Bit 76543210

URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL UCSRC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 1 0 0 0 0 1 1 0

Table 63. UMSEL Bit Settings

UMSEL Mode

0 Asynchronous Operation

1 Synchronous Operation

Table 64. UPM Bits Settings

UPM1 UPM0 Parity Mode

00Disabled

0 1 (Reserved)

1 0 Enabled, Even Parity

1 1 Enabled, Odd Parity

Table 65. USBS Bit Settings

USBS Stop Bit(s)

01-bit

12-bit

1 2 ... 153 154 155 156 157 158 159 160 161 162 163 ... 297 298

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