Rainbow-electronics ATmega161L Manuale Utente Scaricare il pdf (Pagina 58)

ATmega161(L)

1228C–AVR–08/02

Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator that runs at 1 MHz.

This is the typical value at V

= 5V. See characterization data for typical values at other

levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval

can be adjusted (see Table 20 for a detailed description). The WDR (Watchdog Reset)

instruction resets the Watchdog Timer. Eight different clock cycle periods can be

selected to determine the reset period. If the reset period expires without another

Watchdog Reset, the ATmega161 resets and executes from the Reset Vector. For tim-

ing details on the Watchdog Reset, refer to page 28.

To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be

followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer

Control Register for details.

Figure 39. Watchdog Timer

Watchdog Timer Control

• Bits 7..5

– Res: Reserved Bits

These bits are reserved bits in the ATmega161 and will always read as zero.

• Bit 4

– WDTOE: Watchdog Turn-off Enable

This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will

not be disabled. Once set, hardware will clear this bit to zero after four clock cycles.

Refer to the description of the WDE bit for a Watchdog disable procedure.

• Bit 3

– WDE: Watchdog Enable

When the WDE is set (one), the Watchdog Timer is enabled and if the WDE is cleared

(zero), the Watchdog Timer function is disabled. WDE can only be cleared if the

Bit 76543210

$21 ($41) –––WDTOE WDE WDP2 WDP1 WDP0 WDTCR

Read/Write R R R R/W R/W R/W R/W R/W

InitialValue00000000

1 2 ... 53 54 55 56 57 58 59 60 61 62 63 ... 158 159

Nessun commento

Rainbow-electronics ATmega161L Manuale Utente Pagina 58