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AT89C4051
1001D–06/01
Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active.
The mode is invoked by software. The content of the on-chip RAM and all the special
functions registers remain unchanged during this mode. The idle mode can be termi-
nated by any enabled interrupt or by a hardware reset.
P1.0 and P1.1 should be set to “0” if no external pullups are used, or set to “1” if external
pullups are used.
It should be noted that when idle is terminated by a hardware reset, the device normally
resumes program execution, from where it left off, up to two machine cycles before the
internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM
in this event, but access to the port pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when Idle is terminated by reset, the instruction following
the one that invokes Idle should not be one that writes to a port pin or to external
memory.
Power-down Mode In the power-down mode the oscillator is stopped and the instruction that invokes
power-down is the last instruction executed. The on-chip RAM and Special Function
Registers retain their values until the power-down mode is terminated. The only exit
from power-down is a hardware reset. Reset redefines the SFRs but does not change
the on-chip RAM. The reset should not be activated before V
CC
is restored to its normal
operating level and must be held active long enough to allow the oscillator to restart and
stabilize.
P1.0 and P1.1 should be set to “0” if no external pullups are used, or set to “1” if external
pullups are used.
Brown-out Detection When V
CC
drops below the detection threshold, all port pins (except P1.0 and P1.1) are
weakly pulled high. When V
CC
goes back up again, an internal Reset is automatically
generated after a delay of typically 15 msec. The nominal brown-out detection threshold
is 2.1V ± 10%.
V
CC
2.1V
2.1V
PORT PIN
INTERNAL RESET
15 msec.
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