Rainbow-electronics ATtiny15L Manuale Utente

1Features• High-performance, Low-power AVR®8-bit Microcontroller• Advanced RISC Architecture– 90 Powerful Instructions – Most Single Clock Cycle Execu

10ATtiny15L1187E–AVR–06/02Figure 11. Single Cycle ALU OperationI/O Memory The I/O space definition of the ATtiny15L is shown in Table 2.System Clock Ø

11ATtiny15L1187E–AVR–06/02Note: 1. Reserved and unused locations are not shown in the table.All ATtiny15L I/O and peripheral registers are placed in t

12ATtiny15L1187E–AVR–06/02• Bit 2 – N: Negative FlagThe Negative Flag N indicates a negative result after the different arithmetic and logicoperations

13ATtiny15L1187E–AVR–06/02The most typical and general program setup for the Reset and Interrupt VectorAddresses are:Address Labels Code Comments$000

14ATtiny15L1187E–AVR–06/02Figure 12. Reset LogicNote: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT(falling).Table

15ATtiny15L1187E–AVR–06/02Notes: 1. On Power-up, the start-up time is increased with typical 0.6 ms.2. “0” means programmed, “1” means unprogrammed.Ta

16ATtiny15L1187E–AVR–06/02Figure 13. “MCU Start-up, RESET Tied to VCCFigure 14. MCU Start-up, RESET Extended ExternallyExternal Reset An External Rese

17ATtiny15L1187E–AVR–06/02Brown-out Detection ATtiny15L has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCClevel during the operat

18ATtiny15L1187E–AVR–06/02MCU Status Register –MCUSRThe MCU Status Register provides information on which reset source caused an MCUReset.• Bit 7..4 –

19ATtiny15L1187E–AVR–06/02Interrupt Handling The ATtiny15L has two 8-bit Interrupt Mask Control Registers: GIMSK (General Inter-rupt Mask Register) an

2ATtiny15L1187E–AVR–06/02Description The ATtiny15L is a low-power CMOS 8-bit microcontroller based on the AVR RISCarchitecture. By executing powerful

20ATtiny15L1187E–AVR–06/02The corresponding interrupt of External Interrupt Request 0 is executed from Programmemory address $001. See also “External

21ATtiny15L1187E–AVR–06/02vector $003) is executed if a compare match A in Timer/Counter1 occurs, i.e., when theOCF1A bit is set (one) in the Timer/Co

22ATtiny15L1187E–AVR–06/02• Bit 1 – TOV0: Timer/Counter0 Overflow FlagThe bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cle

23ATtiny15L1187E–AVR–06/02• Bits 4, 3 – SM1, SM0: Sleep Mode Select Bits 1 and 0These bits select between the three available sleep modes, as shown in

24ATtiny15L1187E–AVR–06/02ADC Noise Reduction Mode When the SM1/SM0 bits are “01”, the SLEEP instruction forces the MCU into the ADCNoise Reduction mo

25ATtiny15L1187E–AVR–06/02Timer/Counters The ATtiny15L provides two general purpose 8-bit Timer/Counters. The Timer/Countershave separate prescaling s

26ATtiny15L1187E–AVR–06/02The Special Function IORegister – SFIOR• Bit 7..3 – Res: Reserved BitsThese bits are reserved bits in the ATtiny15L and alwa

27ATtiny15L1187E–AVR–06/02Figure 20. Timer/Counter0 Block DiagramThe Timer/Counter0 ControlRegister – TCCR0• Bits 7..3 – Res: Reserved BitsThese bits

28ATtiny15L1187E–AVR–06/02The Timer Counter 0 – TCNT0The Timer/Counter0 is implemented as an up-counter with read and write access. If theTimer/Counte

29ATtiny15L1187E–AVR–06/02The Timer/Counter1 contains two Output Compare Registers, OCR1A and OCR1B, asthe data source to be compared with the Timer/C

3ATtiny15L1187E–AVR–06/02Block Diagram Figure 1. The ATtiny15L Block DiagramPROGRAMCOUNTERINTERNALOSCILLATORWATCHDOGTIMERSTACKPOINTERPROGRAMFLASHHARDW

30ATtiny15L1187E–AVR–06/02• Bits 3, 2, 1, 0 – CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0The Clock Select bits 3, 2, 1, and 0 define the

31ATtiny15L1187E–AVR–06/02Timer/Counter1 OutputCompare RegisterA – OCR1AThe Output Compare Register 1A is an 8-bit read/write register.The Timer/Count

32ATtiny15L1187E–AVR–06/02Figure 22. Effects of Unsynchronized OCR LatchingDuring the time between the write and the latch operation, a read from OCR1

33ATtiny15L1187E–AVR–06/02The frequency of the PWM will be Timer Clock Frequency divided by OCR1B value + 1.The exact duty-cycle of the non-inverted P

34ATtiny15L1187E–AVR–06/02The Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator that runs at 1 MHz.This is the typical v

35ATtiny15L1187E–AVR–06/021. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” mustbe written to WDE even though it is set to

36ATtiny15L1187E–AVR–06/02EEPROM Read/WriteAccessThe EEPROM Access Registers are accessible in the I/O space.The write access time is in the range of

37ATtiny15L1187E–AVR–06/02The EEPROM ControlRegister – EECR• Bit 7..4 – RES: Reserved BitsThese bits are reserved bits in the ATtiny15L and will alway

38ATtiny15L1187E–AVR–06/02The user should poll the EEWE bit before starting the read operation. If a write operationis in progress when new data or ad

39ATtiny15L1187E–AVR–06/02The AnalogComparatorThe Analog Comparator compares the input values on the positive pin PB0 (AIN0) andnegative pin PB1 (AIN1

4ATtiny15L1187E–AVR–06/02Pin DescriptionsVCC Supply voltage pin.GND Ground pin.Port B (PB5..PB0) Port B is a 6-bit I/O port. PB4..0 are I/O pins that

40ATtiny15L1187E–AVR–06/02• Bit 3 – ACIE: Analog Comparator Interrupt EnableWhen the ACIE bit is set (one) and the I-bit in the Status Register is set

41ATtiny15L1187E–AVR–06/02The Analog-to-DigitalConverter, AnalogMultiplexer, and GainStagesFeatures • 10-bit Resolution• ±2 LSB Absolute Accuracy• 0.5

42ATtiny15L1187E–AVR–06/02Figure 25. Analog-to-Digital Converter Block SchematicOperation The ADC converts an analog input voltage to a 10-bit digital

43ATtiny15L1187E–AVR–06/02mode, the ADC is constantly sampling and updating the ADC Data Register. The ADFRbit in ADCSR selects between the two availa

44ATtiny15L1187E–AVR–06/02the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler keeps runningfor as long as the ADEN bit is set, and

45ATtiny15L1187E–AVR–06/02Figure 28. ADC Timing Diagram, Single ConversionFigure 29. ADC Timing Diagram, Free Running ConversionSign and MSB of Result

46ATtiny15L1187E–AVR–06/02ADC Noise CancelerFunctionThe ADC features a noise canceler that enables conversion during ADC Noise Reduc-tion mode (see “S

47ATtiny15L1187E–AVR–06/02• Bits 4..3 – Res: Reserved BitsThese bits are reserved bits in the ATtiny15L and always read as zero.• Bits 2..0 – MUX2..MU

48ATtiny15L1187E–AVR–06/02channel must be selected before entering Free Running mode. Selecting an activechannel after entering Free Running mode may

49ATtiny15L1187E–AVR–06/02The ADC Data Register –ADCL and ADCHADLAR = 0ADLAR = 1When an ADC conversion is complete, the result is found in these two r

5ATtiny15L1187E–AVR–06/02ATtiny15LArchitecturalOverviewThe fast-access Register File concept contains 32 x 8-bit general purpose working reg-isters wi

50ATtiny15L1187E–AVR–06/02ADC Noise-cancelingTechniquesDigital circuitry inside and outside the ATtiny15L generates EMI, which might affect theaccurac

51ATtiny15L1187E–AVR–06/02I/O Port B All AVR ports have true read-modify-write functionality when used as general digital I/Oports. This means that th

52ATtiny15L1187E–AVR–06/02PORT B as General Digital I/O The lower five pins in Port B are equal when used as digital I/O pins.PBn, general I/O pin: Th

53ATtiny15L1187E–AVR–06/02• MISO/OC1A/AIN1 – PORT B, Bit 1In Serial Programming mode, this pin serves as the serial data output, MISO.In Normal mode,

54ATtiny15L1187E–AVR–06/02MemoryProgrammingProgram and DataMemory Lock BitsThe ATtiny15L MCU provides two Lock bits that can be left unprogrammed, “1”

55ATtiny15L1187E–AVR–06/02Calibration Byte The ATtiny15L has a one-byte calibration value for the internal RC Oscillator. This byteresides in the high

56ATtiny15L1187E–AVR–06/02High-voltage SerialProgramming AlgorithmTo program and verify the ATtiny15L in the High-voltage Serial Programming mode, the

57ATtiny15L1187E–AVR–06/02Table 25. High-voltage Serial Programming Instruction Set for ATtiny15L(1)InstructionInstruction FormatOperation RemarksInst

58ATtiny15L1187E–AVR–06/02Note: 1. a = address high bitsb = address low bitsi =dataino = data outx = don’tcare1= Lock Bit12= Lock Bit23 = CKSEL0 Fuse4

59ATtiny15L1187E–AVR–06/02High-voltage SerialProgrammingCharacteristicsFigure 32. High-voltage Serial Programming TimingLow-voltage SerialDownloadingB

6ATtiny15L1187E–AVR–06/02A flexible interrupt module has its control registers in the I/O space with an additionalGlobal Interrupt Enable bit in the S

60ATtiny15L1187E–AVR–06/02The device is clocked from the internal clock at the uncalibrated minimum frequency(0.8 - 1.6 MHz). The minimum low and high

61ATtiny15L1187E–AVR–06/02Data Polling When a byte is being programmed into the Flash or EEPROM, reading the addresslocation being programmed will giv

62ATtiny15L1187E–AVR–06/02Note: 1. a = address high bitsb = address low bitsH =0– low byte, 1 – high byteo = data outi =datainx = don’tcare1= Lock bit

63ATtiny15L1187E–AVR–06/02Low-voltage SerialProgrammingCharacteristicsFigure 35. Low-voltage Serial Programming TimingTable 28. Low-voltage Serial Pro

64ATtiny15L1187E–AVR–06/02Electrical CharacteristicsAbsolute Maximum RatingsOperating Temperature... -55°Cto+125°C*NOTI

65ATtiny15L1187E–AVR–06/02Note: 1. “Max” means the highest value where the pin is guaranteed to be read as low.2. “Min” means the lowest value where t

66ATtiny15L1187E–AVR–06/02TypicalCharacteristicsThe following charts show typical behavior. These data are characterized but not tested.All current co

67ATtiny15L1187E–AVR–06/02Figure 37. Idle Supply Current vs. VCCFigure 38. Calibrated Internal RC Oscillator Frequency vs. VCC00.511.522.532.5 3 3.5 4

68ATtiny15L1187E–AVR–06/02Figure 39. Bandgap Voltage vs. VCCFigure 40. Analog Comparator Offset Voltage vs. Common Mode VoltageNote: 1. Analog Compara

69ATtiny15L1187E–AVR–06/02Figure 41. Analog Comparator Offset Voltage vs. Common Mode VoltageFigure 42. Analog Comparator Input Leakage Current0246810

7ATtiny15L1187E–AVR–06/02The Program and DataAddressing ModesThe ATtiny15L AVR RISC Microcontroller supports powerful and efficient addressingmodes. T

70ATtiny15L1187E–AVR–06/02Figure 43. Watchdog Oscillator Frequency vs. VCCNote: 1. Sink and source capabilities of I/O ports are measured on one pin a

71ATtiny15L1187E–AVR–06/02Figure 45. Pull-up Resistor Current vs. Input VoltageFigure 46. I/O Pin Sink Current vs. Output Voltage0510152025300 0.5 1 1

72ATtiny15L1187E–AVR–06/02Figure 47. I/O Pin Source Current vs. Output VoltageFigure 48. I/O Pin Sink Current vs. Output Voltage024681012141618200 0.5

73ATtiny15L1187E–AVR–06/02Figure 49. I/O Pin Source Current vs. Output VoltageFigure 50. I/O Pin Input Threshold Voltage vs. VCC01234560 0.5 1 1.5 2 2

74ATtiny15L1187E–AVR–06/02Figure 51. I/O Pin Input Hysteresis vs. VCC00.020.040.060.080.10.120.140.160.182.7 4.0 5.0Input hysteresis (V)V ccI/O PIN IN

75ATtiny15L1187E–AVR–06/02ATtiny15L Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page$3F SREG I T H S V N Z C page 11$

76ATtiny15L1187E–AVR–06/02ATtiny15L Instruction Set SummaryMnemonic Operands Description Operation Flags # ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD

77ATtiny15L1187E–AVR–06/02CBI P, b Clear Bit in I/O Register I/O(P,b) ← 0 None 2LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1LSR Rd L

78ATtiny15L1187E–AVR–06/02Ordering InformationPower Supply Speed (MHz) Ordering Code Package Operation Range2.7 - 5.5V 1.6 ATtiny15L-1PCATtiny15L-1SC8

79ATtiny15L1187E–AVR–06/02Packaging Information8P310.16(0.400)9.017(0.355)PIN17.11(0.280)6.10(0.240).300 (7.62) REF5.33(0.210) MAX254(0.100) BSC 0.381

8ATtiny15L1187E–AVR–06/02Operands are contained in register r (Rr) and d (Rd). The result is stored in register d(Rd).I/O Direct Figure 7. I/O Direct

80ATtiny15L1187E–AVR–06/028S22325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 8S2, 8-lead, 0.209" Body, Plastic Small Outline Packag

1ATtiny15L1187E–AVR–06/02Table of ContentsFeatures... 1P

2ATtiny15L1187E–AVR–06/02I/O Port B ... 51Memory Programming

Printed on recycled paper.© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those expressly contain

9ATtiny15L1187E–AVR–06/02Constant byte address is specified by the Z-register contents. The 15 MSBs select wordaddress (0 - 511), and LSB selects low