Rainbow-electronics ATmega128L Manuale Utente Scaricare il pdf (Pagina 28)

100

101

ATmega128(L)

2467B–09/01

Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1

(1)

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper

sector) or SRW00 (lower sector).

The ALE pulse in period T5 is only present if the next instruction accesses the RAM

(internal or external).

Figure 15. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0

(1)

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper

sector) or SRW00 (lower sector).

The ALE pulse in period T6 is only present if the next instruction accesses the RAM

(internal or external).

ALE

T1 T2 T3

Write

Read

A15:8

AddressPrev. addr.

DA7:0

Address DataPrev. data XX

DA7:0 (XMBK = 0)

DataPrev. data Address

DA7:0 (XMBK = 1)

System Clock (CLK

CPU

)

ALE

T1 T2 T3

Write

Read

A15:8

AddressPrev. addr.

DA7:0

Address DataPrev. data XX

DA7:0 (XMBK = 0)

DataPrev. data Address

DA7:0 (XMBK = 1)

System Clock (CLK

CPU

)

T4 T5

1 2 ... 23 24 25 26 27 28 29 30 31 32 33 ... 330 331

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