Rainbow-electronics ATR0620 Manuale Utente Pagina 1

Features•Utilizes the ARM7TDMI™ ARM® Thumb® Processor Core– High-performance 32-bit RISC Architecture– High-density 16-bit Instruction Set– Embedded I

104574CS–GPS–05/05ATR0620 [Preliminary] 4. EBI: External Bus InterfaceThe EBI generates the signals that control the access to the external memory o

114574CS–GPS–05/05 ATR0620 [Preliminary] 7. USART2: Universal Synchronous/ Asynchronous Receiver/TransmitterThe ATR0620 provides three identical, ful

124574CS–GPS–05/05ATR0620 [Preliminary] 12. SF: Special FunctionThe ATR0620 provides registers that implement the following special functions:• Chip

134574CS–GPS–05/05 ATR0620 [Preliminary] 18. Package Outline CTBGA100 17. Ordering InformationExtended Type Number Package RemarksATR0620-100 CTBGA10

144574CS–GPS–05/05ATR0620 [Preliminary] 19. Package CPGA144TOP VIEWBOTTOM VIEW1.575 ± 0.161.575 ± 0.16SIDE VIEW0.018 ± 0.0020.090 ± 0.0090.100 TYP1.

Printed on recycled paper.4574CS–GPS–05/05© Atmel Corporation 2005. All rights reserved. Atmel®, logo and combinations thereof, Everywhere You Are® a

24574CS–GPS–05/05ATR0620 [Preliminary] 1. DescriptionThe GPS baseband processor ATR0620 includes a 16-channel GPS correlator and is based on the ARM

34574CS–GPS–05/05 ATR0620 [Preliminary] Figure 1-1. Block Diagram EmbeddedICEInterface toOff-Chip Memory(EBI)SRAM128KROM288KBRIDGEJTAGASBPDC2USART0 U

44574CS–GPS–05/05ATR0620 [Preliminary] Table 1-1. Pin Configuration Serial Number BGA 100 CPGA 144 Pin NameFirmware LabelPIO Bank A PIO Bank B IOIO

54574CS–GPS–05/05 ATR0620 [Preliminary] 46 B5 B7 EM_A6 (1) (1) (1) (1) (1)47 B4 A3 EM_A7 (1) (1) (1) (1) (1)48 B2 B1 EM_A8 (1) (1) (1) (1) (1)49 D4 F

64574CS–GPS–05/05ATR0620 [Preliminary] 92 H2 N3 P20 1PPS SCK2 SCK2 (1) 1PPS93 E2 J3 P27 GPSMODE11 (1) NPCS1 (1) GPS_MON1194 G1 M1 P28 EM_A20 (1) NPC

74574CS–GPS–05/05 ATR0620 [Preliminary] 138 (1) A7 TMON21 (1) (1) (1) (1) (1)139 (1) B6 TMON22 (1) (1) (1) (1) (1)140 (1) Q5 TMON23 (1) (1) (1) (1) (

84574CS–GPS–05/05ATR0620 [Preliminary] GPSGPSMODE0-12 GPS mode I/O – PIO-controlled after reset SIGHI – Input – –SIGLO – Input – –SIGHI2 – Input –

94574CS–GPS–05/05 ATR0620 [Preliminary] 2. Architecture OverviewThe ATR0620 architecture consists of two main buses, the Advanced System Bus (ASB) an