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DS1543

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DS1543 BLOCK DIAGRAM Figure 1

DS1543 OPERATING MODES Table 1

CE OE WE

DQ0-DQ7 A0-A12 MODE POWER

X X HIGH-Z X DESELECT STANDBY

WRITE ACTIVE

OUT

READ ACTIVE

In Tolerance

HIGH-Z A

READ ACTIVE

BAT

< V

Tolerance

X X X HIGH-Z X DESELECT CMOS STANDBY

BAT

X X X HIGH-Z X DATA

RETENTION

BATTERY

CURRENT

DATA READ MODE

The DS1543 is in the read mode whenever CE (chip enable) is low and WE (write enable) is high. The

device architecture allows ripple through access to any valid address location. Valid data will be

available at the DQ pins within t

after the last address input is stable, providing that CE and OE access

times are satisfied. If

CE or OE access times are not met, valid data will be available at the latter of chip

enable access (t

CEA

) or at output enable access time (t

OEA

). The state of the data input/output pins (DQ) is

controlled by

CE and OE . If the outputs are activated before t

, the data lines are driven to an

intermediate state until t

. If the address inputs are changed while CE and OE remain valid, output data

will remain valid for output data hold time (t

) but will then go indeterminate until the next address

access.

DATA WRITE MODE

The DS1543 is in the write mode whenever WE and CE are in their active state. The start of a write is

referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout

the cycle.

CE and WE must return inactive for a minimum of t

prior to the initiation of a subsequent

read or write cycle. Data in must be valid t

prior to the end of the write and remain valid for t

afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be

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Rainbow-electronics DS1543 Manuale Utente Pagina 3

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